Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
DETAILED ACTION
Election/ Restrictions
Applicant's election of group II without traverse: claims 1-17, in the “Response to Election / Restriction Filed - 04/23/2026”, withdrawal of non-elected claim(s) 18-20 is/are acknowledged. This office action considers claims 1-20, in “Claims - 12/26/2023”, pending for prosecution, of which claim(s) 18-20 is/are withdrawn.
Priority
Acknowledgment is made of applicant's claim for foreign benefit based on KR10-2023-0067116 filed on 05/24/2023.
Claim Rejections - 35 USC § 102
The following is a quotation of 35 U.S.C. 102(a)(1) that forms the basis for the rejection set forth in this Office action:
(a) NOVELTY; PRIOR ART.—A person shall be entitled to a patent unless—
(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention;
Notes: when present, semicolon separated fields within the parenthesis (; ;) represent, for example, as (30A; Fig 2B; [0128]) = (element 30A; Figure No. 2B; Paragraph No. [0128]). For brevity, the texts “Element”, “Figure No.” and “Paragraph No.” shall be excluded, though; additional clarification notes may be added within each field. The number of fields may be fewer or more than three indicated above. These conventions are used throughout this document.
Claims 1-8 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Chang et al. (US 20200212006 A1 – hereinafter Chang).
Regarding Claim 1, Chang teaches a semiconductor package (see the entire document; Figs. 2A-2H; specifically, ([0019] - [0034]), and as cited below), comprising:
a first redistribution layer structure ({11, 12} – Fig. 2H – [0024]);
a first semiconductor die (110 – [0024]) disposed on the first redistribution layer structure ({11, 12});
a second semiconductor die (120 – [0024]) disposed adjacent to the first semiconductor die (110) on the first redistribution layer structure ({11, 12});
a molding material (130 – [0027]) positioned on the first redistribution layer structure ({11, 12}), and covering the first semiconductor die (110) and the second semiconductor die (120);
a bridge die (160 – [0030) positioned on the molding material (130), the first semiconductor die (110), and the second semiconductor die (120), and electrically connecting the first semiconductor die (110) and the second semiconductor die (120) to each other (see [0030] for 160 electrically connecting to 110 and 120);
a substrate (190 – [0034]) positioned on the molding material (130), the first semiconductor die (110), and the second semiconductor die (120), and at least partially surrounding the bridge die (160); and
a second redistribution layer structure (CT={CT1, CT2} – [0019]) disposed on the bridge die (160) and the substrate (190).
Regarding Claim 2, Chang teaches the semiconductor package of claim 1, wherein the substrate (190) includes an embedded trace substrate (ETS) (since 190 embeds traces 194a as shown in Fig. 2E).
Regarding Claim 3, Chang teaches the semiconductor package of claim 1, wherein the bridge die includes a silicon bridge ([0030]).
Regarding Claim 4, Chang teaches the semiconductor package of claim 1, wherein the first semiconductor die and the second semiconductor die exchange signals through the bridge die ([0030]).
Regarding Claim 5, Chang teaches the semiconductor package of claim 1, wherein the bridge die is positioned on a portion of an upper surface of the first semiconductor die and on a portion of an upper surface of the second semiconductor die (as shown in Fig. 2H).
Regarding Claim 6, Chang teaches the semiconductor package of claim 1, wherein the first semiconductor die and the second semiconductor die each include a through silicon via (TSV) (114, 124 – [0025]).
Regarding Claim 7, Chang teaches the semiconductor package of claim 1, wherein the first semiconductor die includes an application processor (AP) ([0026]).
Regarding Claim 8, Chang teaches the semiconductor package of claim 1, wherein the second semiconductor die includes a memory semiconductor ([0026]).
REASON FOR ALLOWANCE
Claims 9-17 are allowed over prior art.
The following is an examiner’s statement of reasons for allowance, which paraphrases and summarizes the claimed invention without intending to be limiting, wherein the legally defined scope of the claimed invention is defined by the allowed claims themselves in view of the written description under 35 USC 112. This statement is not intended to necessarily state all the reasons for allowance or all the details why the claims are allowed and has not been written to specifically or impliedly state that all the reasons for allowance are set forth (MPEP 1302.14).
Regarding claim 9, the reference(s) of the Prior Art of record and considered pertinent to the applicant's disclosure and to the examiner’s knowledge do(es) not teach or render obvious, at least to the skilled artisan, the instant invention regarding a method in their entirety (the individual limitations may be found just not in combination with proper motivation).
The most relevant prior art reference(s) (US 20200212006 A1 to Chang) substantially teach(es) some of limitations in claim 9 as indicated in the in the rejection of claim 1, but not the limitations of “a plurality of conductive posts disposed on the first redistribution layer structure; a first molding material positioned on the first redistribution layer structure and covering the first semiconductor die, the second semiconductor die, and the plurality of conductive posts; an interposer positioned on the first molding material, the plurality of conductive posts, the first semiconductor die, and the second semiconductor die; a third semiconductor die disposed on the interposer; a fourth semiconductor die disposed adjacent to the third semiconductor die on the interposer; and a second molding material positioned on the interposer, and covering the third semiconductor die and the fourth semiconductor die” as recited in claim 9. Therefore, the claim 9 is deemed patentable over the prior art.
Regarding claims 10-17, they are allowed due to their dependencies on claim 9.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to MOHAMMAD A. RAHMAN whose telephone number is (571) 270-0168 and email is mohammad.rahman5@uspto.gov. The examiner can normally be reached on Mon-Fri 8:00-5:00 PM.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Julio J. Maldonado can be reached on (571) 272-1864. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of an application may be obtained from the Patent Application Information Retrieval (PAIR) system. Status information for published applications may be obtained from either Private PAIR or Public PAIR. Status information for unpublished applications is available through Private PAIR only. For more information about the PAIR system, see https://ppair-my.uspto.gov/pair/PrivatePair. Should you have questions on access to the Private PAIR system, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative or access to the automated information system, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/MOHAMMAD A RAHMAN/
Primary Examiner, Art Unit 2898
Prosecution Insights