CTNF 18/395,839 CTNF 79076 DETAILED ACTION Election/Restriction Applicant's election without traverse of Group I, claims 1-17 is acknowledged. Claims 18 - 20 withdrawn from further consideration by the examiner, 37 CFR. 1.142(b), as being drawn to non-elected invention. Specification 06-11 AIA 2. The title of the invention is not descriptive. A new title is required that is clearly indicative of the invention to which the claims are directed. Claim Rejections - 35 USC § 102 07-07-aia AIA 07-07 The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action: A person shall be entitled to a patent unless – 07-08-aia AIA (a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention. 07-15-aia AIA Claim(s) 1, 4, 5, 7, 9 - 17 is/are rejected under 35 U.S.C. 102 (a)(1) as being anticipated by Yu et al. (20210366854) . With regard to claim 1, Yu et al. disclose a semiconductor package (for example, see fig. 15), comprising: a first three-dimensional integrated circuit structure (68A; for example, see paragraph [0049]) on a substrate (a layer 22 functions as a substrate); and a second three-dimensional integrated circuit structure (68B; for example, see paragraph [0049]) on the substrate (22), wherein the first three-dimensional integrated circuit structure (68A) comprises: a first interposer (referred to as “76A1” by examiner’s annotation shown in fig. 15 below) is a first semiconductor die (the first interposer 76A1 is one of the semiconductor chips); and a second semiconductor die (84A) on the first interposer (76A1), wherein the second three-dimensional integrated circuit structure (68B) comprises: a second interposer (referred to as “76A2” by examiner’s annotation shown in fig. 15 below) is a third semiconductor die (the second interposer 76A2 is one of the semiconductor chips); and a fourth semiconductor die (84B) on the second interposer (76A2), wherein the substrate (22) comprises an electrical routing (60) configured to relay (communicate) a signal (a signal of pads “P1” as shown in fig. 15; or a conductive layer 87) from the second semiconductor die (84A) and a signal (a signal of pads “P1” as shown in fig. 15; or a conductive layer 87) from the fourth semiconductor die (84B). PNG media_image1.png 533 804 media_image1.png Greyscale With regard to claim 4, Yu et al. disclose the first semiconductor die (76A1) and the third semiconductor die (76A2) comprise a silicon interposer (interposers 76A1, 76A2 may also include semiconductor substrates 76, respectively wherein semiconductor material inherently including silicon material). With regard to claim 5, Yu et al. disclose the silicon interposer (interposers 76A1, 76A2 may also include semiconductor substrates 76, respectively wherein semiconductor material inherently including silicon material) comprises a plurality of through-silicon vias (78). With regard to claim 7, Yu et al. disclose the second semiconductor die (84A) comprises system-on-chip (a system 88, on (on a bottom surface), chip (a semiconductor substrate, forming in the die 84A, functions as a chip)). With regard to claim 9, Yu et al. disclose the first three-dimensional integrated circuit structure (68A) further comprises a first molding material (referred to as “80A1” by examiner’s annotation shown in fig. 15 below) that molds the second semiconductor die (84A1) on the first semiconductor die (the first interposer 76A1 is the first semiconductor die); and the second three-dimensional integrated circuit structure (68B) further comprises a second molding material (referred to as “80A2” by examiner’s annotation shown in fig. 15 below) that molds the fourth semiconductor die (80B) on the third semiconductor die (the second interposer 76A2 is the third semiconductor die). PNG media_image2.png 531 795 media_image2.png Greyscale With regard to claim 10, Yu et al. disclose a semiconductor package (for example, see fig. 15), comprising: a plurality of first connection members (referred to as “72A1” by examiner’s annotation shown in fig. 15 below; wherein the first connection members 72A1 are portions of the conductive layers 72) electrically connecting a first three-dimensional integrated circuit structure (68A; for example, see paragraph [0049]) on a substrate (a layer 22 functions as a substrate); and a plurality of second connection members (referred to as “72A2” by examiner’s annotation shown in fig. 15 below; wherein the second connection members 72A2 are portions of the conductive layers 72) electrically connecting a second three-dimensional integrated circuit structure (68B; for example, see paragraph [0049]) to the substrate (22); wherein the first three-dimensional integrated circuit structure (68A) comprises: a first interposer (referred to as “76A1” by examiner’s annotation shown in fig. 15 below) is a first semiconductor die (the first interposer 76A1 is one of the semiconductor chips); a second semiconductor die (84A) on the first interposer (76A1), and a plurality of third connection members (referred to as “72A3” by examiner’s annotation shown in fig. 15 below) electrically connecting the second semiconductor die (84A) to the first interposer (76A1) wherein the second three-dimensional integrated circuit structure (68B) comprises: a second interposer (referred to as “76A2” by examiner’s annotation shown in fig. 15 below) is a third semiconductor die (the second interposer 76A2 is one of the semiconductor chips); a fourth semiconductor die (84B) on the second interposer (76A2); and a plurality of fourth connection members (referred to as “72A4” by examiner’s annotation shown in fig. 15 below) electrically connecting the fourth semiconductor die (84B) to the second interposer (76A2), and wherein the substrate (22) comprises an electrical routing (60) configured to relay (communicate) a signal (a signal at one end of a conductive layer 87) from the second semiconductor die (84A) and a signal (a signal at another end of a conductive layer 87) from the fourth semiconductor die (84B). PNG media_image3.png 587 869 media_image3.png Greyscale With regard to claim 11, Yu et al. disclose a pitch (referred to as “A1” by examiner’s annotation shown in fig. 15 below) of neighboring first connection members (72A1) among the plurality of first connection members (72A1) is larger than a pitch (referred to as “A2” by examiner’s annotation shown in fig. 15 below) of neighboring third connection members (72A3) among the plurality of third connection members (72A3); and a pitch (referred to as “A3” by examiner’s annotation shown in fig. 15 below) of neighboring second connection members (72A3) among the plurality of second connection members (72A3) is larger than a pitch (referred to as “A4” by examiner’s annotation shown in fig. 15 below) of neighboring fourth connection members (72A4) among the plurality of fourth connection members (72A4). PNG media_image4.png 543 781 media_image4.png Greyscale With regard to claim 12, Yu et al. disclose the plurality of first connection members (72A1) and the plurality of second connection members (72A2) functions as conductive bumps. With regard to claim 13, Yu et al. disclose the plurality of third connection members (72A3) and the plurality of fourth connection members (72A4) having any micro size of bumps functions as micro-bumps. With regard to claim 14, Yu et al. disclose a first insulation member (one insulating portion of the insulating layers 70 functions as a first insulation member) disposed between the substrate (22) and the first three-dimensional integrated circuit structure (68A), and configured to surround the plurality of first connection members (72A1); and a second insulation member (another insulating portion of the insulating layers 70 functions as a second insulation member) disposed between the substrate (22) and the second three-dimensional integrated circuit structure (68B), and configured to surround the plurality of second connection members (72A2). PNG media_image3.png 587 869 media_image3.png Greyscale With regard to claim 15, Yu et al. disclose the first insulation member (one insulating portion of the insulating layers 70 functions as a first insulation member) and the second insulation member (another insulating portion of the insulating layers 70 functions as a second insulation member) functions as a molded under-fill. With regard to claim 16, Yu et al. disclose the first three-dimensional integrated circuit structure (68A) further comprises a third insulation member (referred to as “89A3” by examiner’s annotation shown in fig. 15 below), wherein the third insulation member (89A3) is disposed between the first interposer (76A1) and the second semiconductor die (84A) and surrounds the plurality of third connection members (72A3); and the second three-dimensional integrated circuit structure (68B) further comprises a fourth insulation member (referred to as “89A4” by examiner’s annotation shown in fig. 15 below), wherein the fourth insulation member (89A4) is disposed between the second interposer (76A2) and the fourth semiconductor die (84B) and surrounds the plurality of fourth connection members (72A4). PNG media_image5.png 583 882 media_image5.png Greyscale With regard to claim 17, Yu et al. disclose the third insulation member (89A3) and the fourth insulation member (89A4) functions as a nonconductive film . Claim Rejections - 35 USC § 103 07-20-aia AIA The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action: A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made. 07-21-aia AIA Claim s 2, 3, 6 are rejected under 35 U.S.C. 103 as being unpatentable over Yu et al. (20210366854) in view of Hu et al. (12593672) . With regard to claim 2, Yu et al. disclose the second interposer (76A2) electrically connects the substrate (22) with the fourth semiconductor die (84B), Yu et al. do not clearly disclose the first semiconductor die is free of active and passive devices; the third semiconductor die is free of active and passive devices. However, Hu et al. disclose the first semiconductor die (an interposer 200A functions as the first semiconductor die) is free of active and passive devices; the third semiconductor die (another interposer 200A functions as the third semiconductor die) is free of active and passive devices. (for example, see column 2, lines 66, 67; column 3, lines 1 – 3, fig. 25). PNG media_image6.png 385 611 media_image6.png Greyscale Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have modified the Yu et al.’s device to have the first semiconductor die is free of active and passive devices; the third semiconductor die is free of active and passive devices as taught by Hu et al. in order to enhance a high electrical connection efficiency between the semiconductor dies and the substate for enhancing a stability operation of the semiconductor device, as is known to one of ordinary skill in the art. With regard to claim 3, Yu et al. do not clearly disclose the substrate comprises an Ajinomoto build-up film substrate. However, Hu et al. disclose the substrate (400) comprises an Ajinomoto build-up film substrate. (for example, see column 11, lines 20 - 37, fig. 25). PNG media_image6.png 385 611 media_image6.png Greyscale Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have modified the Yu et al.’s device to have the substrate comprises an Ajinomoto build-up film substrate as taught by Hu et al. in order to minimize the signal interference for enhancing a stability operation of the semiconductor device. With regard to claim 6, Yu et al. do not clearly disclose the first interposer and the second interposer further comprise a redistribution layer structure, respectively. However, Hu et al. disclose the first interposer (200A) and the second interposer (another interposer 200A functions as the second interposer) further comprise a redistribution layer structure (240), respectively. (for example, see column 13, lines 21 - 22, figs. 20, 25). PNG media_image7.png 239 790 media_image7.png Greyscale PNG media_image6.png 385 611 media_image6.png Greyscale Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have modified the Yu et al.’s device to have the first interposer and the second interposer further comprise a redistribution layer structure, respectively as taught by Hu et al. in order to enhance a high electrical connection efficiency between the semiconductor dies and the substate for enhancing a stability operation of the semiconductor device, as is known to one of ordinary skill in the art . 07-21-aia AIA Claim 8 is rejected under 35 U.S.C. 103 as being unpatentable over Yu et al. (20210366854) in view of Lai et al. (12557645) . With regard to claim 8, Yu et al. do not clearly disclose the fourth semiconductor die comprises a high bandwidth memory. However, Lai et al. disclose the fourth semiconductor die (a semiconductor die 107 functions as the fourth semiconductor die) comprises a high bandwidth memory. (for example, column 3, lines 29 – 31, fig. 1). PNG media_image8.png 366 768 media_image8.png Greyscale Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have modified the Yu et al.’s device to have the fourth semiconductor die comprises a high bandwidth memory as taught by Hu et al. in order to support data-intensive computations for enhancing a stability operation of the semiconductor device, as is known to one of ordinary skill in the art. Conclusion 8. Any inquiry concerning this communication or earlier communications from the examiner should be directed to TAN N TRAN whose telephone number is (571) 272 - 1923. The examiner can normally be reached on 8:30-5:00PM. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Davienne Monbleau can be reached on (571) 272-1945. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of an application may be obtained from the Patent Application Information Retrieval (PAIR) system. Status information for published applications may be obtained from either Private PAIR or Public PAIR. Status information for unpublished applications is available through Private PAIR only. For more information about the PAIR system, see http://pair-direct.uspto.gov. Should you have questions on access to the Private PAIR system, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative or access to the automated information system, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /TAN N TRAN/ Primary Examiner, Art Unit 2812 Application/Control Number: 18/395,839 Page 2 Art Unit: 2812 Application/Control Number: 18/395,839 Page 3 Art Unit: 2812 Application/Control Number: 18/395,839 Page 4 Art Unit: 2812 Application/Control Number: 18/395,839 Page 5 Art Unit: 2812 Application/Control Number: 18/395,839 Page 6 Art Unit: 2812 Application/Control Number: 18/395,839 Page 7 Art Unit: 2812 Application/Control Number: 18/395,839 Page 8 Art Unit: 2812 Application/Control Number: 18/395,839 Page 9 Art Unit: 2812
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