Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
DETAILED ACTION
Amendment filed on 5/19/26 has been entered.
Response to Arguments
Applicant's arguments with respect to the amendment have been fully considered but are not persuasive. The prior art of record continues to teach or suggest the amended limitations. The detailed basis for maintaining the rejection in view of the amendment is provided below.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
Claim 12 is rejected under 35 U.S.C. 112(b) as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor regards as the invention.
The claim recites "a first direction" and "a second direction perpendicular to the first direction." However, claim 1, from which claim 12 ultimately depends, already recites a first direction and a second direction. It is unclear whether the "first direction" and "second direction" recited in claim 12 refer to the first direction and second direction previously recited in claim 1 or instead introduce a new first direction and a new second direction. As a result, the metes and bounds of claim 12 cannot be determined with reasonable certainty. Accordingly, claim 12 is indefinite.
For purposes of examination and notwithstanding the indefiniteness discussed above, the claim 12 is interpreted under the broadest reasonable interpretation as encompassing the first direction and second direction previously recited in claim 1.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claims 1-8, 11-12 and 14 are rejected under 35 U.S.C. 102 (a)(1)/(a)(2) as being anticipated by Sasaki (US 20200381327).
Regarding claim 1, Figs. 2 and 5 of Sasaki disclose a semiconductor device 1 comprising:
an insulated substrate 10 [0041] whose upper surface is exposed to an outside of molding portion 30 (Fig 2, [0046]);
a semiconductor chip 20 [0040] formed on a lower if the insulated substrate (Fig 2);
a drain connection lead 42 (Fig. 2; [0043]: lead 42 connected to drain electrode 21) comprising a first part and a second part, the first part of the drain connection lead forming, on a lower surface of insulated substrate 10, a junction with the insulated substrate extending along a first direction (Y direction in Fig. 5, extending between 42 and 52) or a second direction (X direction in Fig. 5, transverse to the first direction) perpendicular to the first direction (e.g., inner lead portions 41M/41c joined to isolated land part 13), and the second part of the drain connection lead forming a terminal configured to be connected to an external device ([0047]-[0050]);
a source connection lead 52 (Fig. 2; [0043]: lead 52 connected to source electrode 22) comprising a first part and a second part, the first part of the source connection lead forming an electrical connection with semiconductor chip 20 through component mounting land part 12, and the second part of the source connection lead forming a terminal configured to be connected to an external device [0051];
wherein the drain connection lead comprises a plurality of inner frames extending along the second direction (Fig. 5),
the plurality of inner frames including a first inner frame 41c and a second inner frame 41a,
the first inner frame is connected to the lower surface of insulated substrate 10 through isolated land part 13 such that, when viewed from the upper-left side of Fig. 5, a right long side of the first inner frame 41c faces a left side of semiconductor chip 20, and
the second inner frame being connected to the lower surface of insulated substrate 10 through semiconductor chip 20 and component mounting land part 12 such that, when viewed from the upper-left side of Fig. 5, a left long side of the second inner frame 41a faces a right side of semiconductor chip 20, as evidenced by inner middle frame 41a extending longitudinally along and being disposed adjacent to the right side of semiconductor chip 20.
Regarding claim 2. Sasaki discloses The semiconductor device of claim 1, wherein:
an upper surface of the semiconductor device is insulated from the drain connection lead (Fig 2, [0046]: by molding portion 30, which is formed of an insulating resin material).
Regarding claim 3. Sasaki discloses The semiconductor device of claim 1, wherein:
the insulated substrate includes:
an upper metal layer 15 [0041]/[0042], a lower metal layer including component mounting land part 12 and isolated land part 13 [0041]/[0042]/[0045], and an insulated layer 11 [0041] disposed between the upper metal layer and the lower metal layer (Fig 2),
an upper surface (Fig 2: the exposed surface of 15a of exposed conductive part 15) of the upper metal layer is exposed to an outside of the molding portion 30 (Fig 2, [0041]), and
a lower surface (Fig 2: the surface of 13 facing 20) of the lower metal layer forms a junction with the drain connection lead (Fig 2, [0048]-[0049]; through isolated land part 13 and inner lead portion 41c).
Regarding claim 4. Sasaki discloses The semiconductor device of claim 1, wherein:
the junction of the drain connection lead formed on a lower surface (Fig 2: the surface of 10 facing 20) of the insulated substrate has,
a shape that extends parallel to a direction in which the other part of the drain connection lead extends (as shown by the alignment of inner lead portions 41c and 41d in Fig 2), or extends in a direction perpendicular to the direction in which the other part of the drain connection lead extends.
Regarding claim 5. Sasaki discloses The semiconductor device of claim 1, wherein:
an upper surface of the drain connection lead includes a plurality of upper surfaces respectively corresponding to a first height, a second height lower than the first height, and a third height lower than the second height (Fig. 5). In particular, the frame portion extending between 41a and 41M is disposed at the first height, the frame portion extending between 41M and 41d is disposed at the second height lower than the first height, and the frame portion including 41c is disposed at the third height lower than the second height.
Regarding claim 6. Sasaki discloses The semiconductor device of claim 1, wherein:
the drain connection lead includes a plurality of frames (Fig 5),
the plurality of frames include,
an outer frame (the outer frame adjacent 42/42a) connected to an external device [0050] and
a middle frame (the frame portion between 41M and 41D, and the protruding frame portion extending from the outer frame toward the 41a, positioned between 41a, the 41c frame portions, and the outer frame) formed between the first and second inner frames and the outer frame (Fig 5).
Regarding claim 7. Sasaki discloses The semiconductor device of claim 6, wherein:
the outer frame is formed to extend along the first direction (Fig 5), and
the outer frame is formed to have a height difference from the middle frame (Fig 5: due to the middle frame in the protruding frame).
Regarding claim 8. Sasaki discloses The semiconductor device of claim 7, wherein:
the first inner frame and the second inner frame are formed to be perpendicular to the outer frame (the first inner frame and the second inner frame extending X direction whereas the outer frame extending in Y direction).
Regarding claim 11. Sasaki discloses The semiconductor device of claim 6, wherein:
a portion of the middle frame is formed to have a height difference from the first inner frame and the second inner frame (Fig 5: refer to the protruding portion).
Regarding claim 12. Sasaki discloses The semiconductor device of claim 6 (see the examiner’s interpretation above regarding the 112(b) rejection), wherein the middle frame comprises a first part (the frame portion extending between 41M and 41d) and a second part (the frame portion extending between 41a and first part), the first part of the middle frame extends from the second part of the middle frame along [[a]] the first direction (Y direction), and then extends along [[a]] the second direction (X direction) perpendicular to the first direction and is connected to the first inner frame 41c and the second inner frame 41a (Fig 5).
Regarding claim 14. Sasaki discloses The semiconductor device of claim 6, wherein:
at least one of the middle frame is formed to be spaced apart from a lower surface of the insulated substrate (as shown in Figs. 2 and 5, where at least a portion of the middle frame extending between frame portions 41M and 41d is elevated relative to insulated substrate 10 and is spaced apart from the lower surface of the insulated substrate).
Conclusion
THIS ACTION IS MADE FINAL. Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any extension fee pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to Changhyun Yi whose telephone number is (571)270-7799. The examiner can normally be reached Monday-Friday: 8A-4P.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Davienne Monbleau can be reached on 571-272-1945. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/Changhyun Yi/Primary Examiner, Art Unit 2812
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