Prosecution Insights
Last updated: April 19, 2026
Application No. 18/396,035

SEMICONDUCTOR DEVICE

Non-Final OA §112
Filed
Dec 26, 2023
Examiner
SEVEN, EVREN
Art Unit
2812
Tech Center
2800 — Semiconductors & Electrical Systems
Assignee
Power Master Semiconductor Co. Ltd.
OA Round
1 (Non-Final)
74%
Grant Probability
Favorable
1-2
OA Rounds
2y 4m
To Grant
82%
With Interview

Examiner Intelligence

Grants 74% — above average
74%
Career Allow Rate
532 granted / 723 resolved
+5.6% vs TC avg
Moderate +8% lift
Without
With
+8.3%
Interview Lift
resolved cases with interview
Typical timeline
2y 4m
Avg Prosecution
29 currently pending
Career history
752
Total Applications
across all art units

Statute-Specific Performance

§101
2.3%
-37.7% vs TC avg
§103
51.9%
+11.9% vs TC avg
§102
23.1%
-16.9% vs TC avg
§112
20.3%
-19.7% vs TC avg
Black line = Tech Center average estimate • Based on career data from 723 resolved cases

Office Action

§112
Detailed Action The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA. Claim Rejections - 35 USC § 112 The following is a quotation of 35 U.S.C. 112(b): (b ) CONCLUSION.— The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention. Claims 1-20 are rejected under 35 U.S.C. 112(b) being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor regards as the invention. Specifically regarding Claims 1 and 13, multiple introductions of “a plurality of semiconductor chips” render the claims indefinite as the multiple introductions add uncertainty regarding exactly what is referred to. Examiner recommends amendments below and commensurate amendments to the remaining claims: 1. A semiconductor device implemented as a semiconductor module package for driving an inverter, the semiconductor device comprising: a first upper metal layer in which a first plurality of semiconductor chips implementing a right phase switching pattern are disposed along a first direction to form a first row; a second upper metal layer in which a second plurality of semiconductor chips implementing a left phase switching pattern are disposed along the first direction to form a second row; a first connection, in the first upper metal layer, connecting [[ a ]] the first plurality of semiconductor chips disposed along the first row to each other in series and to the second upper metal layer in parallel; and a second connection, in the second upper metal layer, connecting [[ a ]] the second plurality of semiconductor chips disposed along the second row to each other in series. Allowable Subject Matter Claims 1-20 would be allowable if rewritten or amended to overcome the rejection(s) under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA), 2nd paragraph, set forth in this Office action. The following is a statement of reasons for the indication of allowable subject matter: The cited prior art (see attached form 892) generally teaches power switching devices, but do not teach the limitations of claims 1 and 13. Conclusion Any inquiry concerning this communication or earlier communications from the examiner should be directed to FILLIN "Examiner name" \* MERGEFORMAT EVREN SEVEN whose telephone number is FILLIN "Phone number" \* MERGEFORMAT (571)270-5666 . The examiner can normally be reached FILLIN "Work Schedule?" \* MERGEFORMAT Mon-Fri 8:00- 5:00 Pacific . Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, FILLIN "SPE Name?" \* MERGEFORMAT Christine Kim can be reached at FILLIN "SPE Phone?" \* MERGEFORMAT (571) 272-8458 . The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /EVREN SEVEN/ Primary Examiner, Art Unit 2812
Read full office action

Prosecution Timeline

Dec 26, 2023
Application Filed
Feb 15, 2026
Non-Final Rejection — §112 (current)

Precedent Cases

Applications granted by this same examiner with similar technology

Patent 12604709
PROBE CARD CONFIGURED TO CONNECT TO A PROBE PAD LOCATED IN SAW STREET OF A SEMICONDUCTOR WAFER
2y 5m to grant Granted Apr 14, 2026
Patent 12598748
THREE-DIMENSIONAL MEMORY DEVICES AND METHODS FOR FORMING THE SAME
2y 5m to grant Granted Apr 07, 2026
Patent 12598701
SEMICONDUCTOR DEVICE WITH SELECTION STRUCTURE AND METHOD FOR FABRICATING THE SAME
2y 5m to grant Granted Apr 07, 2026
Patent 12586736
MEMS SWITCH
2y 5m to grant Granted Mar 24, 2026
Patent 12588324
PACKAGE STRUCTURE AND FORMING METHOD THEREOF
2y 5m to grant Granted Mar 24, 2026
Study what changed to get past this examiner. Based on 5 most recent grants.

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Prosecution Projections

1-2
Expected OA Rounds
74%
Grant Probability
82%
With Interview (+8.3%)
2y 4m
Median Time to Grant
Low
PTA Risk
Based on 723 resolved cases by this examiner. Grant probability derived from career allow rate.

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