CTNF 18/396,150 CTNF 100436 Notice of Pre-AIA or AIA Status 07-03-aia AIA 15-10-aia The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA. Information Disclosure Statement The information disclosure statement (IDS) submitted on 04/10/2026 and 12/26/2023 are in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statement is being considered by the Examiner. Election/Restrictions Applicant’s election of claims 1-5, 7-10 and 13 without traverse in the reply filed on 05/22/2026 is acknowledged. Claim Rejections - 35 USC § 103 07-20-aia AIA The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action: A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made. 07-21-aia AIA Claim s 1, 9-10, and 13 are rejected under 35 U.S.C. 103 as being unpatentable over Mizutani et al US 20220399358 A1 in view of Su et al US 20200006152 A1. Mizutani et al and Su et al will be referenced to as Mizutani and Su respectively henceforth . Regarding Claim 1, Mizutani teaches: “A semiconductor structure comprising: a memory die comprising a three-dimensional memory device (memory die 900, [0115, 0120], FIG. 27: 900 contains a three dimensional memory array.) ; and a logic die bonded to the memory die (second logic die 600, [0186, 0189], FIG. 27) , wherein the logic die comprises a word line switching circuit ([0187], FIG. 27: 620 comprises word line drivers.) ” Mizutani doesn’t substantially teach: “containing a fin field effect transistor including a semiconductor fin and a first gate dielectric having a first gate dielectric thickness, and further comprises a first additional field effect transistor including a second gate dielectric having a second gate dielectric thickness that is different from the first gate dielectric thickness.” However, Su teaches: “containing a fin field effect transistor (Su: [0015], FIG. 2L: the various transistors may be planar FETs or FINFETs. The device region 102 may be a flash memory region and 108 a core region. One of ordinary skill in the art would understand that a flash memory region is connected to word lines. 102 may comprise FINFETs. 108 may comprise planar-FETs.) including a semiconductor fin (Su: [0015]: a FINFET must have a semiconductor fin to be a FINFET.) and a first gate dielectric (Su: tunnel oxide layer 126a, [0021], FIG. 2A) having a first gate dielectric thickness (Su: FIG. 2A) , and further comprises a first additional field effect transistor (Su: device region 108, [0015], FIG. 2L) including a second gate dielectric (Su: gate dielectric 138c, [0022], FIG. 2A) having a second gate dielectric thickness that is different from the first gate dielectric thickness (Su: FIG. 2L) .” It would have been obvious to one with ordinary skill in the art before the effective filing date of the invention to recognize that the device of Mizutani is modifiable in view of Su by incorporating the logic circuit design of Su into Mizutani. This is because Su teaches the details of forming a logic circuit region for a flash device. Flash devices are a kind of EEPROM device. One of ordinary skill in the art would be motivated to incorporate a logic circuit region design in order to properly form their device as Mizutani does not provide the detail needed to form a logic circuit region. Regarding Claim 9, Mizutani/Su teaches: “The semiconductor structure of Claim 1, wherein: the first additional field effect transistor comprises a planar-FET gate electrode comprising a first gate electrode material and having a first gate height (Su: gate electrode 140a, [0022], FIG. 2A, FIG. 2L) ; and the fin field effect transistor comprises a finFET gate electrode comprising a second gate electrode material and having a second height that is higher than the first height (Su: control gate layer 132a, [0021], FIG. 2A, FIG. 2L: 132a may comprise polysilicon. Gate electrode 140a may comprise a capping layer comprising titanium. Titanium is not polysilicon.) .” Regarding Claim 10, Mizutani/Su teaches: “The semiconductor structure of Claim 1, wherein: the fin field effect transistor comprises a finFET gate electrode (Su: control gate layer 132a, [0021], FIG. 2A, FIG. 2L: 132a may comprise polysilicon.) and a first dielectric gate spacer that laterally surrounds the finFET gate electrode (Su: gate spacer 144a, [024], FIG. 2A, FIG. 2L) ; the first additional field effect transistor comprises a planar-FET gate electrode (Su: gate electrode 140c, [0022], FIG. 2A, FIG. 2L) and a second dielectric gate spacer that laterally surrounds the planar-FET gate electrode (Su: gate spacers 144e, [0024], FIG. 2A, FIG. 2L) ; and the first dielectric gate spacer and the second dielectric gate spacer comprise a same dielectric material (Su: [0024]: 144a and 144e may both comprise silicon oxide. Silicon oxide is a dielectric.) .” Regarding Claim 13, Mizutani/Su teaches: “The semiconductor structure of Claim 1, wherein: the logic die comprises a logic-side semiconductor substrate (Mizutani: second logic-side substrate 609, [0191], FIG. 27) ; the semiconductor fin and a semiconductor active region of the first additional field effect transistor comprise portions of the logic-side semiconductor substrate (Su [0017]: the fin of the FINFET in 102 is made from a part of semiconductor substrate 110.) ; the logic die comprises logic-side bonding pads (Mizutani: second logic-side bonding pads 696, [0194], FIG. 27) embedded within logic-side dielectric material layers (Mizutani: backside dielectric material layers 610, FIG. 27) ; and the memory die comprises memory-side bonding pads (Mizutani: memory-side bonding pads 196, [0194], FIG. 27) that are embedded within memory-side dielectric material layers (Mizutani: stepped dielectric material portion 65, [0176], FIG. 27) and bonded to the logic-side bonding pads (Mizutani: [0189], FIGs. 26-27) .” 07-22-aia AIA Claim 2 is rejected under 35 U.S.C. 103 as being unpatentable over Mizutani/Su as applied to claim s 1, 9-10 and 13 above, and further in view of Shih et al US 20200243544 A1. Shih et al will be referenced to as Shih henceforth . Regarding Claim 2, Mizutani/Su teaches: “The semiconductor structure of Claim 1,” Mizutani/Su doesn’t substantially teach: “wherein the semiconductor fin comprises tapered upper corners.” However, Shih teaches: “wherein the semiconductor fin comprises tapered upper corners (Shih: [0059], FIG: 6B: the upper corners of the fins are tapered.) .” It would have been obvious to one with ordinary skill in the art before the effective filing date of the invention to recognize that the device of Mizutani/Su is modifiable in view of Shih by rounding the upper corners of the semiconductor fin of the FINFET in Mizutani/Su. This is because Shih teaches that rounded top surfaces of semiconductor fins provide an improvement to device performance (Shih: [0059]) . 07-21-aia AIA Claim s 1 and 3 are rejected under 35 U.S.C. 103 as being unpatentable over Mizutani in view of Su and Tsuda et al US 20200211909 A1. Tsuda et al will be referenced to as Tsuda respectively henceforth . Regarding Claim 1, Mizutani teaches: “A semiconductor structure comprising: a memory die comprising a three-dimensional memory device (memory die 900, [0115, 0120], FIG. 27: 900 contains a three dimensional memory array.) ; and a logic die bonded to the memory die (second logic die 600, [0186, 0189], FIG. 27) , wherein the logic die comprises a word line switching circuit ([0187], FIG. 27: 620 comprises word line drivers.) ” Mizutani doesn’t substantially teach: “containing a fin field effect transistor (Su: [0015], FIG. 2L: the various transistors may be planar FETs or FINFETs. The device region 102 may be a flash memory region and 108 a core region. One of ordinary skill in the art would understand that a flash memory region is connected to word lines. 102 may comprise FINFETs.) ” However, Su teaches: “containing a fin field effect transistor (Su: [0015], FIG. 2L: the various transistors may be planar FETs or FINFETs. The device region 102 may be a flash memory region and 108 a core region. One of ordinary skill in the art would understand that a flash memory region is connected to word lines. 102 may comprise FINFETs.) ” Mizutani further doesn’t substantially teach: “including a semiconductor fin and a first gate dielectric having a first gate dielectric thickness, and further comprises a first additional field effect transistor including a second gate dielectric having a second gate dielectric thickness that is different from the first gate dielectric thickness.” However, Tsuda/Su teaches: “including a semiconductor fin (Su/Tsuda: Tsuda: well WEL, [0099], annotated FIG. 15 #1) and a first gate dielectric (Tsuda: gate insulating film IF3, [0100], FIG. 8, FIG. 15) having a first gate dielectric thickness (Tsuda: FIG. 15) , and further comprises a first additional field effect transistor (Tsuda: MISFET Q2, FIG. 15) including a second gate dielectric (Tsuda: gate insulating film IF2, [0108]) having a second gate dielectric thickness that is different from the first gate dielectric thickness (Tsuda: FIG. 15) .” It would have been obvious to one with ordinary skill in the art before the effective filing date of the invention to recognize that the device of Mizutani is modifiable in view of Tsuda and in further view of Su by incorporating the logic circuit design of Tsuda into Mizutani and further including the FINFET design of Su into Tsuda. This is because Tsuda teaches the details of forming a word line circuit (Tsuda: [0103]) . One of ordinary skill in the art would be motivated to incorporate a logic circuit region design in Mizutani in order to properly form their device. Further, one of ordinary skill in the art would be motivated to further combine Su with Mizutani/Tsuda because neither Mizutani nor Tsuda teaches which kinds of transistor may be used in a flash memory region. Su however teaches that a FINFET may be used in a flash memory region of a logic circuit. Therefore, one of ordinary skill in the art would be motivated to make the transistor used in a flash memory region of Mizutani/Tsuda to be a FINFET. PNG media_image1.png 350 542 media_image1.png Greyscale Annotated FIG. 15 #1 Regarding Claim 3, Mizutani/Su/Tsuda teaches: “The semiconductor structure of Claim 1, further comprising: a first dielectric isolation layer laterally surrounding the semiconductor fin (Tsuda: isolation portion ST, [0041], FIG. 6, FIG. 15) ; and a second dielectric isolation layer laterally surrounding a semiconductor active region of the first additional field effect transistor (Tsuda: insulating film IL1, FIG. 15) , wherein a bottom surface of the first dielectric isolation layer and a bottom surface of the second dielectric isolation layer are located within a same horizontal plane (Tsuda: annotated FIG. 15 #1) .” Allowable Subject Matter 12-151-08 AIA 07-43 12-51-08 Claim s 4-5 and 7-8 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims. Regarding Claim 4, Both Mizutani/Tsuda and Mizutani/Su/Shih fail to explicitly teach : “wherein a top surface of the second dielectric isolation layer is located above a first horizontal plane including a top surface of the first dielectric isolation layer, and below a second horizontal plane including a topmost surface of the semiconductor fin” In view of the rest of the limitations of claim 3. Both Mizutani/Tsuda and Mizutani/Su/Shih fail to explicitly teach the above limitation because the limitation cannot be found in the prior art of record. This is because Mizutani does not describe the details of a word line circuit region. Further, Tsuda does not teach the above limitation because the horizontal plane including the top surface of the first dielectric isolation layer of Tsuda is above the second horizontal plane including a topmost surface of the semiconductor fin of Tsuda. Therefore, the top surface of the second dielectric layer must be above the horizontal plane including a topmost surface of the semiconductor fin. Su does not teach the above limitation because Su does not teach the limitations of claim 3. Shih does not remedy these deficiencies. The Examiner did not find prior art which one of ordinary skill in the art would use alone or would find obvious to combine with the invention of either Mizutani/Tsuda or Mizutani/Su/Shih to reach all of the limitations of the claim. Regarding Claim 5, Both Mizutani/Tsuda and Mizutani/Su/Shih fail to explicitly teach : “wherein the first additional field effect transistor comprises a planar transistor, and wherein the second gate dielectric is located entirely below a horizontal plane including a topmost surface of the semiconductor fin” In view of the rest of the limitations of claim 1. Mizutani/Tsuda and Mizutani/Su/Shi fail to explicitly teach the above limitation because the limitation cannot be found in the prior art of record. This is because Mizutani does not describe the details of a word line circuit region. Further, Tsuda does not teach the above limitation because the second gate dielectric is located entirely above a semiconductor fin. In Su, the second gate dielectric is in the same horizontal plane as a topmost surface of the semiconductor fin. Shih does not remedy these deficiencies. The Examiner did not find prior art which one of ordinary skill in the art would use alone or would find obvious to combine with the invention of either Mizutani/Tsuda or Mizutani/Su/Shih to reach all of the limitations of the claim. Regarding Claim 7, Both Mizutani/Tsuda and Mizutani/Su/Shih fail to explicitly teach : “an interface between the lower planar-FET gate electrode portion and the upper planar-FET gate electrode portion is located entirely within a horizontal plane including a topmost surface of the semiconductor fin” In view of the rest of the limitations of claim 1. Mizutani/Tsuda and Mizutani/Su/Shih fail to explicitly teach the above limitation because the limitation cannot be found in the prior art of record. This is because Mizutani/Tsuda and Mizutani/Su/Shih do not teach a lower planar-FET gate electrode portion and an upper planar-FET gate electrode portion. The Examiner did find other art which nearly meets the limitation, such as US 10109638 B1, however this art does not explicitly include a FINFET, and explicitly includes alternative transistor structures with distinctive geometries such as a SOI transistor. Therefore it is not clear that it meets the above limitation. The Examiner did not find prior art which one of ordinary skill in the art would use alone or would find obvious to combine with the invention of either Mizutani/Tsuda or Mizutani/Su/Shih to reach all of the limitations of the claim. Regarding Claim 8, this claim depends on claim 7 and is objectionable for the same reasons. Conclusion Any inquiry concerning this communication or earlier communications from the examiner should be directed to ALEXANDRE XAVIER RAMIREZ whose telephone number is (571)272-2715. The examiner can normally be reached Monday - Friday 8:30 AM to 6:00 PM. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, William Partridge can be reached at (571) 270-1402. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /ALEXANDRE X RAMIREZ/Examiner, Art Unit 2812 /William B Partridge/Supervisory Patent Examiner, Art Unit 2812 Application/Control Number: 18/396,150 Page 2 Art Unit: 2812 Application/Control Number: 18/396,150 Page 3 Art Unit: 2812 Application/Control Number: 18/396,150 Page 4 Art Unit: 2812 Application/Control Number: 18/396,150 Page 5 Art Unit: 2812 Application/Control Number: 18/396,150 Page 6 Art Unit: 2812 Application/Control Number: 18/396,150 Page 7 Art Unit: 2812 Application/Control Number: 18/396,150 Page 8 Art Unit: 2812 Application/Control Number: 18/396,150 Page 9 Art Unit: 2812 Application/Control Number: 18/396,150 Page 10 Art Unit: 2812 Application/Control Number: 18/396,150 Page 11 Art Unit: 2812 Application/Control Number: 18/396,150 Page 12 Art Unit: 2812
Prosecution Insights