DETAILED ACTION
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claims 1-20 are pending.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims c are rejected under 35 U.S.C. 102(a)(1) as being anticipated by US 9,496,032 to Kyung (hereafter Kyung).
Regarding independent claim 1, Kyung teaches a circuit comprising:
a plurality of sets of memory cells, wherein individual sets of memory cells of the plurality of sets of memory cells are coupled to a respective local bit line (LBL) (FIG. 1: cell blocks 110 coupled to respective local bit line LBL via bit line BL0 in column direction);
a multiplexer with inputs coupled to the respective LBLs, wherein the multiplexer is to couple a selected one of the LBLs to a LBL merge node (FIG. 1: GYSW 170 coupling LBLs to GBL), wherein the selected LBL is coupled to a first set of memory cells of the plurality of memory cells; and
read circuitry coupled to the LBL merge node to read data from a first memory cell of the first set of memory cells via the selected LBL (FIG. 1: WD/SA 160, see 4:25-28).
Regarding dependent claim 2, Kyung teaches wherein the multiplexer includes respective transistors coupled between the respective inputs of the multiplexer and LBL merge node (FIG. 2: transistor 172 for each of the LBLs).
Regarding dependent claim 4, Kyung implicitly teaches wherein the LBLs for the respective sets of memory cells are in at least two metal layers of the circuit (FIG. 2: one layer corresponding to BL0 and the other layer corresponding to LBL).
Regarding dependent claim 5, Kyung implicitly teaches wherein all of the LBLs except one are kept in a floating state between read operations (because only the selected LBL corresponding to column address is turned-on and precharged through GBL in response to read command, see 4:13-19).
Regarding dependent claim 6, Kyung teaches wherein, to read the data from the first memory cell, the read circuitry is to precharge the selected LBL via the multiplexer while the other LBLs are maintained in the floating state (because only the selected LBL corresponding to column address is turned-on and precharged through GBL in response to read command, see 4:13-19).
Regarding dependent claim 7, Kyung implicitly teaches wherein the selected LBL is precharged to a voltage that corresponds to a supply voltage, Vcc, minus a transistor threshold voltage, Vt (predetermined level of a voltage is provided to SWL and applied to BL via GBL and LBL, see 4:1-19. It is understood that voltage applied to SWL is often supply voltage Vcc. Since Vcc is applied to BL via LBL, and to LBL via GBL, voltage on LBL equal to Vcc minus a transistor threshold voltage 172).
Claims 1-3 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by US 8,605,532 to Kajigaya et al. (hereafter Kayjigaya).
Regarding independent claim 1, Kajjigaya teaches a circuit comprising:
a plurality of sets of memory cells, wherein individual sets of memory cells of the plurality of sets of memory cells are coupled to a respective local bit line (LBL) (FIG. 24: e.g. memory cells coupled to local bit line LBL0);
a multiplexer with inputs coupled to the respective LBLs, wherein the multiplexer is to couple a selected one of the LBLs to a LBL merge node (FIG. 24: comprising transistors receiving signals SW0-SW3, coupling LBL0-LBL3 to input node of GBA via GBL), wherein the selected LBL is coupled to a first set of memory cells of the plurality of memory cells (FIG. 24: e.g. selected LBL0 is coupled to MC0); and
read circuitry coupled to the LBL merge node to read data from a first memory cell of the first set of memory cells via the selected LBL (FIG. 23: global sense amplifier GSA).
Regarding dependent claim 2, Kajigaya teaches wherein the multiplexer includes respective transistors coupled between the respective inputs of the multiplexer and LBL merge node (FIG. 23: transistors receiving signals SW0-SW3).
Regarding dependent claim 3, Kajigaya teaches wherein the read circuitry (see FIG. 48) includes a precharge circuitry (FIG. 48: precharge circuit 45) and a keeper circuitry coupled to the LBL merge node (FIG. 48: keeper circuitry comprising transistors Q60-Q61).
Claims 1, 9 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by US 6,345,010 to Shimazaki et al. (hereafter Shimazaki).
Regarding independent claim 1, Shimazaki teaches a circuit comprising:
a plurality of sets of memory cells, wherein individual sets of memory cells of the plurality of sets of memory cells are coupled to a respective local bit line (LBL) (FIG. 1: for BANK1, each column of memory cells coupled to respective local bit lines LBL0-LBL3 in BANK1);
a multiplexer with inputs coupled to the respective LBLs, wherein the multiplexer is to couple a selected one of the LBLs to a LBL merge node (FIG. 2: for BANK1, comprising transistors MP13, MP15, MP17 and MP19 for coupling to input node on line RGBL), wherein the selected LBL is coupled to a first set of memory cells of the plurality of memory cells; and
read circuitry coupled to the LBL merge node to read data from a first memory cell of the first set of memory cells via the selected LBL (FIG. 4: sense amp. SA, which has input coupled to RGBL).
Regarding dependent claim 9, Shimazaki teaches one or more processor cores, wherein the memory cells correspond to cache memory for the one or more processor cores (see Field of the Invention).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 17-18, 20 are rejected under 35 U.S.C. 103 as being unpatentable over Kyung in view of Shimazaki in view of Kayjigaya
Regarding independent claim 17, Kyung teaches a system comprising:
memory circuitry
a plurality of sets of bitcells, wherein individual sets of bitcells are coupled to a respective local bit line (LBL) of a plurality of LBLs (FIG. 1: cell blocks 110 coupled to respective local bit line LBL via bit line BL0 in column direction); and
a multiplexer coupled between the merge node and the plurality of LBLs, wherein, for a read operation to read data from a first bitcell that is coupled to a first LBL of the plurality of LBLs (FIG. 1: GYSW 170 coupling LBLs to GBL), the multiplexer is to selectively couple the first LBL to the read merge node and keep the other LBLs in a floating state (because only the selected LBL corresponding to column address is turned-on and precharged through GBL in response to read command, see 4:13-19).
However, Kyung does not teach the strikethrough limitations.
Shimazaki teaches Shimazaki teaches one or more processor cores, wherein the memory cells correspond to cache memory for the one or more processor cores (see Field of the Invention).
Kajigaya teaches a read merge circuitry (see FIG. 48) includes a precharge circuitry (FIG. 48: precharge circuit 45) and a keeper circuitry coupled to the LBL merge node (FIG. 48: keeper circuitry comprising transistors Q60-Q61).
Since Kyung and Shimazaki and Kajigaya are all from the same field of endeavor, the purpose disclosed by Kyung and Kajigaya would have been recognized in the pertinent art of Shimazaki.
It would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to:
use the memory device of Kyung as cache memory for processor cores of Shimazaki in order to improve in operational speed (see 1:23-25 and 4:59-64).
use the read merge circuitry of Kajigaya for Kyung because it is an available design.
Regarding dependent claim 18, Kyung teaches wherein, for the read operation, the control circuitry is to: precharge global bit line GBL, control the multiplexer to selectively couple the first LBL to the GBL to precharge the first LBL to a second voltage that is less than the first voltage (FIG. 2: applying predetermined voltage to BL via LBL, and to LBL via GBL, voltage on LBL equal to Vcc minus a transistor threshold voltage 172, see 4:1-19).
Kajigaya teaches precharge the merge node, via the precharge circuitry, to a first voltage (FIG. 48: via precharge circuit 45).
Regarding dependent claim 20, Kyung teaches one or more of a power supply interface, a communication interface, or a display coupled to the one or more processor cores (see FIG. 6).
Allowable Subject Matter
Claim 8 is objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Claims 10-16 are allowed.
The following is a statement of reasons for the indication of allowance:
The prior art made of record and considered pertinent to the applicant's disclosure does not teach or suggest the claimed invention having the following limitations, in combination with the remaining claimed limitations.
With respect to dependent claim 8: wherein, to read the data from the first memory cell, a read word line coupled between the first memory cell is turned on after the selected LBL is precharged.
With respect to independent claim 10: the control circuitry is to: … activate a read word line associated with the first bitcell after the first LBL is precharged.
With respect to dependent claim 19: wherein the first bitcell is coupled to a first LBL via a transistor that is controlled by a read word line, and wherein the control circuitry is further to activate the read word line to turn on the transistor after the first LBL is precharged.
Conclusion
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January 16, 2026
/VANTHU T NGUYEN/Primary Examiner, Art Unit 2824