DETAILED ACTION
This action is responsive to the application filed on 12/26/2023. Claims 1-20 are pending and have been examined.
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Specification
The title of the invention is not descriptive. A new title is required that is clearly indicative of the invention to which the claims are directed. The examiner suggests the applicant amend the title with details of operand register reuse.
Claim Objections
Claim 6 is objected to because of the following informalities:
In regards to claim 6, line 32 of the page amend “at least one criterion” to “at least one condition” as to use language consistent with claim 4, line 12 of the page and correct a minor antecedent basis issue as there is no prior recitation of “criterion”. (note this issue is addressed as an objection because it does not rise to the level of indefiniteness as defined in 35 USC 112(b))
Appropriate correction is required.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 1, 12-15 and 20 is/are rejected under 35 U.S.C. 103 as being unpatentable over Hickey, PGPUB No. 2013/0138925 (cited on IDS filed on 12/4/2024) and further in view of NPL reference “Storageless Value Prediction Using Prior Register Values” hereby referred to as Tullsen.
In regards to claim 1, Hickey discloses An apparatus (See Fig. 5, processor (element 200)) comprising: a register file comprising a plurality of registers to store operand data for instructions ([0067-0069]: wherein a register file (element 210) comprises a plurality of registers that store operand data for instructions (See Fig. 5)) execution circuitry to execute, in response to an instruction which references a given source register, a data processing operation on pre-processed operand data obtained after a preprocessing action has been performed using stored operand data from the given source register of the register file ([0015, 0068-0070, and 0080]: wherein floating point execution unit (element 208) executes a data processing operation corresponding to an instruction, which references a source register including a denormal operand, on pre-processed operand data obtained after normalizing (preprocessing action) has been performed to normalize the denormal operand data stored in the source register (also see [0013-0014] for more details related to preprocessing actions)) a pre-processed operand data buffer separate from the register file, the pre-processed operand data buffer being accessible to the execution circuitry and configured to store preprocessed operand data corresponding to a subset of the plurality of registers ([0070-0071 and 0079]: wherein a scratch register file (element 218) stores preprocessed operand data corresponding to unprocessed data in a subset of registers in register file (element 210), and is separate from register file (element 210). Wherein scratch register file is accessible by floating point execution unit (element 208) as illustrated in Fig. 5 ([also see [0013-0014] for more details related to preprocessing actions)) and register reuse detection circuitry to: detect a register reuse opportunity for a subsequent instruction which references a reused source register also referenced by a previous instruction for which pre-processed operand data corresponding to the reused source register was written to the preprocessed operand data buffer ([0070, 0073 and 0078-0079]: wherein register file preprocessor (element 222) performs the operations (elements 250 of Fig.7) which detect a register reuse opportunity (see elements 254, 258, 260 and 256) for a subsequent instruction which references a denormal operand stored in a reused source register also referenced by a previous pre-normalization instruction for which pre-normalized (preprocessed) the denormal operand corresponding to the reused source register and stored the pre-normalized data to scratch register file (element 218) (also see [0014, 0024 and 0026] for further details about subsequent instructions reference pre-processed data. Also note the registers storing the denormal values in the register file 210 are reused registers because such registers are first used/referenced by speculative pre-processing instructions and then reused/re-referenced by subsequent instructions)) and in response to detecting the register reuse opportunity, control the execution circuitry to execute the data processing operation for the subsequent instruction using the pre-processed operand data stored in the pre-processed operand data buffer corresponding to the reused source register ([0028 and 0079]: in response to detecting the register reuse opportunity (elements 254, 256, 258 and 260) the floating point execution unit will execute the floating point instruction for the subsequent instruction using the operand data stored in scratch register corresponding to reused source register in register file (element 210)) and suppress the pre-processing action from being performed for the subsequent instruction in relation to stored operand data from the reused source register of the register file. ([0026, 0028 and 0079]: wherein pre-normalization action is suppressed from being performed for the subsequent instruction (e.g. instruction executes without having to preprocess the data) in relation to the stored denormal operand data in the reused register of the register file (element 210). Instruction instead references pre-processed data in corresponding scratch register)
Hickey does not disclose register reuse detection to detect register reuse opportunity when it is guaranteed that no intervening instruction between the previous instruction and the subsequent instruction will cause a write to the reused source register.
Tullsen discloses register reuse detection to detect register reuse opportunity when it is guaranteed that no intervening instruction between the previous instruction and the subsequent instruction will cause a write to the reused source register. (see page 272: “Our scheme currently exploits that only when profiling finds the stored value still in a register, but more aggressive compilation could ensure that correlated stores and loads use the same register without intervening writes of the register” (see Fig. 2 which additionally discloses correlating instructions to allow same register reuse))
It would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to modify the register reuse detection circuitry in Hickey to allow register reuse between instructions when it is guaranteed that no writes occur between first and subsequent instructions which target a same register as taught in Tullsen. It would have been obvious to one of ordinary skill in the art because ensuring that no intervening writes exists ensures no overwrites occur to the register before the subsequent instruction can access the data in the register, thus guaranteeing the correct data required by the subsequent instruction is available for reuse.
Claim 20 is similarly rejected on the same basis as claim 1 above as claim 20 is the computer-readable medium corresponding to the apparatus of claim 1 above. (Note: Hickey [0038] discloses a computer readable medium)
In regards to claim 12, the combination of Hickey and Tullsen discloses The apparatus according to claim 1 (see rejection of claim 12 above) comprising selection circuitry to select, as the subset of the plurality of registers for which the pre-processed operand data buffer stores the preprocessed operand data, one or more registers which are referenced as source registers by instructions of at least one predetermined class of instructions. (Hickey [0013, 0070 and 0073-0074]: wherein scavenger logic (in preprocessor circuitry element 222) selects, as the subset of registers for which the scratch register file stores preprocessed operand data, one or more registers are referenced as source registers by instructions of at least a one predetermined class of instructions. Wherein the instructions can be of an instruction class that operates on normalized, decrypted or compressed values. Or alternatively instructions are of a floating-point instruction class (See Fig. 6))
In regards to claim 13, the combination of Hickey and Tullsen discloses The apparatus according to claim 1 (see rejection of claim 1 above) in which the pre-processing action suppressed in response to detecting the register reuse opportunity comprises reading of the stored operand data from the given source register of the register file. (Hickey [0028 and 0079]: wherein the pre-processed action suppressed comprises reading the stored operand data from register file (element 210) because the instruction is modified to reference the pre-processed data in the scratch register filed)
In regards to claim 14, the combination of Hickey and Tullsen discloses The apparatus according to claim 1 (see rejection of claim 1 above) in which the pre-processing action suppressed response to detecting the register reuse opportunity comprises transfer of the stored operand data from the given source register to the execution circuitry. (Hickey [0079]: wherein the pre-processed action suppressed comprises transferring the stored operand data in register file (element 210) to execution circuitry because the pre-processed data is transferred from scratch register file (element 218) to the execution unit (See Figs. 5 and 7))
In regards to claim 15, the combination of Hickey and Tullsen discloses The apparatus according to claim 1 (see rejection of claim 1 above) in which the pre-processing action suppressed in response to detecting the register reuse opportunity comprises re-formatting the stored operand data to generate the pre-processed operand data. (Hickey [0026 and 0079]: wherein the pre-processed action suppressed comprises not normalizing the stored operand data to generate the pre-processed operand data because the instruction utilizes the pre-processed data already stored in scratch register file)
Claim(s) 2 is/are rejected under 35 U.S.C. 103 as being unpatentable over Hickey, Tullsen and further in view of Guiterrez, PGPUB No. 2021/0173650 (cited on IDS filed on 12/4/2024).
In regards to claim 2, the combination of Hickey and Tullsen discloses The apparatus according to claim 1 (see rejection of claim 1 above) in which the register reuse detection circuitry is configured to: determine that the register reuse opportunity exists for the subsequent instruction as it is guaranteed that no intervening instruction between the previous instruction and the subsequent instruction will cause a write to the reused source register. (Hickey [0070, 0073 and 0078-0079]: wherein register file preprocessor (element 222) performs the operations (elements 250 of Fig.7) which detect a register reuse opportunity (see elements 254, 258, 260 and 256) for a subsequent instruction which references a denormal operand stored in a reused source register also referenced by a previous pre-normalization instruction for which pre-normalized (preprocessed) the denormal operand corresponding to the reused source register and stored the pre-normalized data to scratch register file (element 218)| Tullsen: see page 272: “Our scheme currently exploits that only when profiling finds the stored value still in a register, but more aggressive compilation could ensure that correlated stores and loads use the same register without intervening writes of the register” (see Fig. 2 which additionally discloses correlating instructions to allow same register reuse) (note: the combination of Hickey and Tullsen as disclosed in claim 1 above teach the above limitation))
The combination of Hickey and Tullsen does not disclose in which the register reuse detection circuitry is configured to: determine whether a number of cycles between the previous instruction referencing the reused source register and the subsequent instruction referencing the reused source register is less than a threshold number of cycles, and in response to determining that the number of cycles between the previous instruction and the subsequent instruction is less than the threshold number.
Gutierrez discloses in which the register reuse detection circuitry is configured to: determine whether a number of cycles between the previous instruction referencing the reused source register and the subsequent instruction referencing the reused source register is less than a threshold number of cycles ([0037-0039]) and in response to determining that the number of cycles between the previous instruction and the subsequent instruction is less than the threshold number, determine that the register reuse opportunity exists for subsequent instruction. ([0039 and 0047]: wherein it is determined if a number of cycles indicated by the reuse distance is less than a threshold number which indicates that a register value is more likely to be used again and thus a reuse opportunity exists for a subsequent instruction)
It would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to modify the register reuse detection circuitry in Hickey and Tullsen to determine if a number of cycles between the two instructions which use a same register are below a threshold as taught in Guiterrez. It would have been obvious to one of ordinary skill in the art because using a prediction technique that uses an operand reuse distance to predict the likely hood that operand data will be reused can be used for benefit of determining when to cache or save such data that will be reused or discard such data (Guiterrez [0038-0039]). Thus, improving overall memory storage and latency in a processor.
Claim(s) 16 is/are rejected under 35 U.S.C. 103 as being unpatentable over Hickey, Tullsen and further in view of Kromer, PGPUB No. 2004/0255099.
In regards to claim 16, the combination of Hickey and Tullsen discloses The apparatus according to claim 15 (see rejection of claim 15 above).
The combination of Hickey and Tullsen does not disclose in which the re-formatting comprises Booth encoding operand data for a multiplication operation. Hickey does generally disclose that any type of preprocessing of data that is unprocessed in a register file such as decrypting, decompressing, etc. can occur. However, Hickey has not explicitly disclosed Booth encoding.
Kromer discloses in which the re-formatting comprises Booth encoding operand data for a multiplication operation. ([0023 and Fig. 2]: wherein a booth encoding stage encodes operand data prior to a multiplication operation at a next stage (element 134))
It would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to modify the re-formatting operations for instructions included in Hickey to include Booth encoding for multiply operations as taught in Kromer. It would have been obvious to one of ordinary skill in the art because it would have been the simple substitution of one known element (including a preprocessing operation including Booth encoding for a multiplication operation as taught in Kromer) for another (including generic preprocessing operations for generic operations as taught in Hickey) to yield predictable results (including a booth encoding re-formatting for operand data use in a multiplication operation) (MPEP 2143, Example B).
Claim(s) 18-19 is/are rejected under 35 U.S.C. 103 as being unpatentable over Hickey, Tullsen and further in view of Ray, PGPUB No. 2023/0104845.
In regards to claim 18, the combination of Hickey and Tullsen discloses A system comprising: the apparatus of claim 1 (Hickey [0067 and Fig. 5]: wherein a system comprises the processor of claim 1).
The combination of Hickey and Tullsen does not disclose apparatus implemented in at least one packaged chip; at least one system component; and a board, wherein the at least one packaged chip and the at least one system component are assembled on the board.
Ray discloses apparatus implemented in at least one packaged chip ([0355]: wherein apparatus implemented in a partially packaged chip is disclosed) at least one system component; and a board ([0355-0357]: wherein at least one system component (one of elements 2491, 2492, 2485, 2487, etc.) and a substrate (board) are disclosed (See Fig. 24C)) wherein the at least one packaged chip and the at least one system component are assembled on the board. ([0355-0357]: wherein at least one system component and at least one partially packaged chip are assembled on the substrate (See Fig. 24C))
It would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to modify the system of Hickey to implemented in packaged assembly as the system of Ray. It would have been obvious to one of ordinary skill in the art because implementing a system in a packaged assembly can offer advantages in space efficiency, cost reduction and improved performance.
In regards to claim 19, the combination of Hickey, Tullsen and Ray discloses A chip-containing product (Ray [0355]: package assembly (element 2490)) comprising the system of claim 18 (see rejection of claim 18 above) assembled on a further board with at least one other product component. (Ray [0243 and 0361]: wherein package assembly can be assembled on a further board with at least one other chipset or multi-chip module)
Allowable Subject Matter
Claims 3-11 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Claim 17 is allowed.
The following is a statement of reasons for the indication of allowable subject matter:
The prior art of record, alone or in combination, fail to disclose or render obvious the claims filed on 12/26/2023. The prior art of record has not taught either individually or in combination and together with all other claimed features “The apparatus according to claim 2, in which the threshold number of cycles corresponds to a minimum number of cycles possible between two instructions which reference a same source register when those two instructions are separated by an intervening instruction which causes a write to that same source register” as claimed in claim 3.
The closest prior art of record, Gutierrez (PGPUB No. 2021/021073650) discloses that if a number cycles between a previous instruction and a subsequent instruction are less than a threshold then it is likely that an operand referenced by the previous instruction will be reused by the subsequent instruction. However, Gutierrez does not disclose “…the threshold number of cycles corresponds to a minimum number of cycles possible between two instructions which reference a same source register when those two instructions are separated by an intervening instruction which causes a write to that same source register” as claimed in claim 3 above.
While, Olson (PGPUB No. 2015/0058572) discloses a threshold closeness value indicating a number of intervening instructions between a first and second instruction which use a same operand. However, Olson does not disclose “…the threshold number of cycles corresponds to a minimum number of cycles possible between two instructions which reference a same source register when those two instructions are separated by an intervening instruction which causes a write to that same source register” as claimed in claim 3 above. Thus, claim 3 is allowable over the prior art.
Furthermore, the prior art of record has not taught either individually or in combination and together with all other claimed features the limitations discussed above. Thus, while some limitations may be broadly disclosed in the references above, the specific combination of limitations would not be obvious as claimed absent impermissible hindsight.
The following is a statement of reasons for the indication of allowable subject matter:
The prior art of record, alone or in combination, fail to disclose or render obvious the claims filed on 12/26/2023. The prior art of record has not taught either individually or in combination and together with all other claimed features “The apparatus according to claim 1, comprising: register-overwriting-enabling circuitry to perform a register-overwriting-enabling action required to have been performed after a read of a given register by an earlier instruction before it is possible that a later instruction could cause overwriting of the given register, where the register overwriting-enabling action is dependent on at least one condition being satisfied; and register-protection-delaying circuitry to apply a register-protection delay period after the at least one condition is determined to be satisfied, to prevent the register-overwriting-enabling circuitry from performing the register-overwriting-enabling action for at least the register protection delay period after the at least one condition has been determined to have been satisfied” as claimed in claim 4.
The closest prior art of record, Burky (PGPUB No. 2024/0111535) discloses reclaim queue circuitry to insert a delay period to prevent a physical register from being reused until such time as it can be accessed by an adjusted child instruction; wherein the delay until a freed physical register can be reused is dependent on the maximum distance (e.g. a number of instructions) between the parent instruction and child instruction. However, Burky does not disclose “The apparatus according to claim 1, comprising: register-overwriting-enabling circuitry to perform a register-overwriting-enabling action required to have been performed after a read of a given register by an earlier instruction before it is possible that a later instruction could cause overwriting of the given register, where the register overwriting-enabling action is dependent on at least one condition being satisfied...” as claimed in claim 4 above. Additionally, Burky is commonly owned and falls under a 102(b)(2)(c) exception and thus cannot be used in a prior art rejection.
Therefore, none of the prior art references of record disclose “…comprising: register-overwriting-enabling circuitry to perform a register-overwriting-enabling action required to have been performed after a read of a given register by an earlier instruction before it is possible that a later instruction could cause overwriting of the given register, where the register overwriting-enabling action is dependent on at least one condition being satisfied; and register-protection-delaying circuitry to apply a register-protection delay period after the at least one condition is determined to be satisfied, to prevent the register-overwriting-enabling circuitry from performing the register-overwriting-enabling action for at least the register protection delay period after the at least one condition has been determined to have been satisfied” as claimed above.
Furthermore, the prior art of record has not taught either individually or in combination and together with all other claimed features the limitations discussed above. Thus, while some limitations may be broadly disclosed in the references above, the specific combination of limitations would not be obvious as claimed absent impermissible hindsight.
Claims 5-11 are dependent upon claim 4 above and therefore are similarly allowable over the prior art at least based upon dependency.
The following is a statement of reasons for the indication of allowable subject matter:
The prior art of record, alone or in combination, fail to disclose or render obvious the claims filed on 12/26/2023. The prior art of record has not taught either individually or in combination and together with all other claimed features “An apparatus comprising: register rename circuitry to perform register renaming to map architectural register identifiers specified by instructions to physical register identifiers indicative of corresponding portions of hardware register storage; register reclaim circuitry to determine when a previously allocated physical register identifier is free to be re-allocated to a new architectural register identifier specified by an instruction awaiting renaming; reclaim delaying circuitry, responsive to the register reclaim circuitry indicating that a given physical register identifier is free to be re-allocated, to prevent the given physical register identifier actually being re-allocated during a protection delay period following the register reclaim circuitry indicating that the given physical register identifier is free to be re-allocated; and protection delay period adjustment circuitry to dynamically adjust a duration of the protection delay period based on at least one feedback indication” as claimed in claim 17 above.
The closest prior art of record, Burky (PGPUB No. 2024/0111535) discloses reclaim queue circuitry to insert a delay period to prevent a physical register from being reused until such time as it can be accessed by an adjusted child instruction; wherein the delay until a freed physical register can be reused is dependent on the maximum distance (e.g. a number of instructions) between the parent instruction and child instruction. However, Burky does not disclose “…and protection delay period adjustment circuitry to dynamically adjust a duration of the protection delay period based on at least one feedback indication...” as claimed in claim 17 above. Additionally, Burky is commonly owned and falls under a 102(b)(2)(c) exception and thus cannot be used in a prior art rejection.
While, Piry (PGPUB No. 2008/0177983) discloses suppressing register rename mapping generations if no pending reads or writes effect a physical register. However, Piry does not disclose “…reclaim delaying circuitry, responsive to the register reclaim circuitry indicating that a given physical register identifier is free to be re-allocated, to prevent the given physical register identifier actually being re-allocated during a protection delay period following the register reclaim circuitry indicating that the given physical register identifier is free to be re-allocated; and protection delay period adjustment circuitry to dynamically adjust a duration of the protection delay period based on at least one feedback indication” as claimed in claim 17 above.
Furthermore, the prior art of record has not taught either individually or in combination and together with all other claimed features the limitations discussed above. Thus, while some limitations may be broadly disclosed in the references above, the specific combination of limitations would not be obvious as claimed absent impermissible hindsight.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure:
Piry (PGPUB No. 2008/0177983) discloses suppressing register rename mapping generations if no pending reads or writes effect a physical register
Burky (PGPUB No. 2024/0111535) discloses reclaim queue circuitry to insert a delay period to prevent a physical register from being reused until such time as it can be accessed by an adjusted child instruction; wherein the delay corresponds with a maximum permitted distance between the parent instruction and the child instruction in the stream of instructions. The delay until a freed physical register can be reused is dependent on the maximum distance (e.g. a number of instructions) between the parent instruction and child instruction.
Olson (PGPUB No. 2015/0058572) discloses a threshold closeness value indicating a number of intervening instructions between a first and second instruction which use a same operand
Any inquiry concerning this communication or earlier communications from the examiner should be directed to COURTNEY P SPANN whose telephone number is (571)431-0692. The examiner can normally be reached M-F, 9am-6pm, EST.
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/COURTNEY P SPANN/ Primary Examiner, Art Unit 2183