DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claim(s) 1-6, 10, 14-16 and 20 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by HSU (US 20200105897).
Regarding claim 1, HSU discloses an electronic device comprising:
a conductive material layer (the channel region 240, see fig 7, para 21);
a ferroelectric layer (the ferroelectric layer comprising 330 and 370, see fig 7, para 28 and 31) covering the conductive material layer (330 covers a bottom surface of 240, see fig 7) and having ferroelectric or antiferroelectric properties (330 and 370 are ferroelectric, see para 28 and 31); and
an electrode layer (fig 7, 400, para 35) covering the ferroelectric layer (400 covers a top surface of 370, see fig 7),
wherein the ferroelectric layer comprises a first oxide layer comprising a first component and having a first thickness (330 can be an HfO layer that is 1-2 nm thick, see fig 7, para 28-29), and
a second oxide layer comprising hafnium and a second component and having a second thickness that is twice or more the first thickness (370 can be HfZnO and be 1.5-5 nm thick, meaning it can be twice a thick as 330, see fig 7, para 31).
Regarding claim 2, HSU discloses the electronic device of claim 1, wherein a ratio of the second thickness to the first thickness is 2:1 to 10:1 (330 can be 1 nm thick and 370 can be 2 nm thick, giving a ratio of 2:1, see para 28 and 31).
Regarding claim 3, HSU discloses the electronic device of claim 1, wherein the first thickness is 1 nm or less, and a total thickness of the ferroelectric layer is 3 nm or less (330 can be 1nm thick and 370 can be 2nm thick, see fig 7, para 28 and 31).
Regarding claim 4, HSU discloses the electronic device of claim 3, wherein the first thickness is 0.2 nm to 1 nm, and the total thickness of the ferroelectric layer is 0.5 nm to 3 nm (330 can be 1nm thick and 370 can be 2nm thick, see fig 7, para 28 and 31).
Regarding claim 5, HSU discloses the electronic device of claim 1, wherein a proportion of the second component is greater than a proportion of the hafnium at a surface of the second oxide layer (370 can be HfZnO with a Zn dopant concentration of 70% which is a majority, see para 32).
Regarding claim 6, HSU discloses the electronic device of claim 5, wherein the proportion of the second component is greater than the proportion of the hafnium in a region of the second oxide layer from the surface to a thickness portion of 1/3 or less (370 can be HfZnO with a Zn dopant concentration of 70% which is a majority, see para 32).
Regarding claim 10, HSU discloses the electronic device of claim 1, wherein the first component and the second component are each at least one of Zr, Si, Al, Y, La, Gd, or Sr (330 and 370 can be HfAlO, meaning Al can be the first component, see fig 7, para 28 and 31).
Regarding claim 14, HSU discloses the electronic device of claim 1, wherein layers are stacked in an order of the first oxide layer, the second oxide layer, and the electrode layer (the layers are stacked in the order of 330, 370, 400, see fig 7), or an order of the second oxide layer, the first oxide layer, and the electrode layer, and
ferroelectric crystallization of the ferroelectric layer is a result of heat treatment performed before and/or after the electrode layer is formed (an anneal can be done after 330 and 370 are formed, see para 34).
Regarding claim 15, HSU discloses the electronic device of claim 1, further comprising: a dielectric layer, that is not ferroelectric, between at least one of the conductive material layer and the ferroelectric layer or the ferroelectric layer and the electrode layer (SiO layer 280 between 330 and 240, see fig 7, para 23).
Regarding claim 16, HSU discloses the electronic device of claim 1, wherein the conductive material layer comprises a channel (240 is a channel, see fig 7, para 21), the electrode layer comprises a gate electrode (400 is a gate electrode, see fig 7, para 35), and the electronic device is at least one of a logic or memory device (the device can be a FET which is a logic device, see fig 7, para 21).
Regarding claim 20, HSU discloses an electronic apparatus comprising
at least one electronic device (the device 200, see fig 7, para 17), the at least one electronic device comprises:
a conductive material layer (the channel region 240, see fig 7, para 21);
a ferroelectric layer (the ferroelectric layer comprising 330 and 370, see fig 7, para 28 and 31) covering the conductive material layer (330 covers a bottom surface of 240, see fig 7) and having ferroelectric or antiferroelectric properties (330 and 370 are ferroelectric, see para 28 and 31); and
an electrode (fig 7, 400, para 35) layer covering the ferroelectric layer (400 covers a top surface of 370, see fig 7),
wherein the ferroelectric layer comprises a first oxide layer comprising a first component (330 can be an HfO layer that is 1-2 nm thick, see fig 7, para 28-29), and a second oxide layer comprising hafnium and a second component (370 can be HfZnO and be 1.5-5 nm thick, meaning it can be twice a thick as 330, see fig 7, para 31).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 7-9 and 11-13 is/are rejected under 35 U.S.C. 103 as being unpatentable over HSU (US 20200105897) in view of YOO (US 20180240804).
Regarding claim 7, HSU discloses the electronic device of claim 5.
HSU fails to explicitly disclose a device, wherein
the first component and the second component are Zr,
the first oxide layer comprises ZrO2, and
the second oxide layer comprises alternating oxides of Hf and Zr.
YOO teaches a device, wherein
the first component and the second component are Zr (the first layer 135a can be a ZrO layer, and the second layer can comprise 125a, 135b, 125b, 135c, 125c, which are alternating layers of HfO 125 and ZrO 135 which comprises ZrO, see fig 3, para 42),
the first oxide layer comprises ZrO2 (the first layer 135a can be a ZrO layer, and the second layer can comprise 125a, 135b, 125b, 135c, 125c, which are alternating layers of HfO 125 and ZrO 135 which comprises ZrO, see fig 3, para 42), and
the second oxide layer comprises alternating oxides of Hf and Zr (the first layer 135a can be a ZrO layer, and the second layer can comprise 125a, 135b, 125b, 135c, 125c, which are alternating layers of HfO 125 and ZrO 135 which comprises ZrO, see fig 3, para 42).
HSU and YOO are analogous art because they both are directed towards FET devices with FE layers and one of ordinary skill in the art would have had a reasonable expectation of success to modify the device of HSU with the FE material layers of YOO because they are from the same field of endeavor.
It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to modify the device of HSU with the FE material layers of YOO in order to control ferroelectric properties (see YOO para 35).
Regarding claim 8, HSU discloses the electronic device of claim 1.
HSU fails to explicitly disclose a device, wherein the second oxide layer comprises alternating oxides of Hf and the second component, and
a proportion of the second component is greater than a proportion of the hafnium at a surface of the second oxide layer.
YOO teaches a device, wherein the second oxide layer comprises alternating oxides of Hf and the second component (the second layer can be 135a, 125b, 135b, 125c and 135c, which are alternating layers of HfO 125 and ZrO 135, see fig 1, para 24), and
a proportion of the second component is greater than a proportion of the hafnium at a surface of the second oxide layer (the tops surface can be 135 which is a ZrO layer not an HfO layer, see fig 1, para 24).
HSU and YOO are analogous art because they both are directed towards FET devices with FE layers and one of ordinary skill in the art would have had a reasonable expectation of success to modify the device of HSU with the FE material layers of YOO because they are from the same field of endeavor.
It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to modify the device of HSU with the FE material layers of YOO in order to control ferroelectric properties (see YOO para 35).
Regarding claim 9, HSU and YOO disclose the electronic device of claim 8.
HSU fails to explicitly disclose a device, wherein the second oxide layer is formed by alternately and repeatedly depositing the hafnium oxide and the oxide of the second component in one cycle or in multiple cycles.
YOO teaches a device, wherein the second oxide layer is formed by alternately and repeatedly depositing the hafnium oxide and the oxide of the second component in one cycle or in multiple cycles (the HfO and ZrO layers are formed in cycles, see fig 7-8, para 60).
HSU and YOO are analogous art because they both are directed towards FET devices with FE layers and one of ordinary skill in the art would have had a reasonable expectation of success to modify the device of HSU with the FE material layers of YOO because they are from the same field of endeavor.
It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to modify the device of HSU with the FE material layers of YOO in order to control ferroelectric properties (see YOO para 35).
Regarding claim 11, HSU discloses the electronic device of claim 10.
HSU fails to explicitly disclose a device, wherein the first component and the second component are the same, and a composition ratio of an oxide of the first component to an oxide of the hafnium is greater than 1 in the ferroelectric layer.
YOO teaches a device, wherein the first component and the second component are the same (the first oxide layer can be 135a which is ZrO and the second oxide layer can be 125a, 135b, 125b 135c, 125c and 135d which are Hf and Zr oxide, see fig 4, para 46), and a composition ratio of an oxide of the first component to an oxide of the hafnium is greater than 1 in the ferroelectric layer (there are more ZrO layers 135 than HfO layers 125, see fig 4, para 46).
HSU and YOO are analogous art because they both are directed towards FET devices with FE layers and one of ordinary skill in the art would have had a reasonable expectation of success to modify the device of HSU with the FE material layers of YOO because they are from the same field of endeavor.
It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to modify the device of HSU with the FE material layers of YOO in order to control ferroelectric properties (see YOO para 35).
Regarding claim 12, HSU and YOO disclose the electronic device of claim 11.
HSU fails to explicitly disclose a device, wherein the first oxide layer comprises ZrO2, and the second oxide layer comprises alternating oxides of the hafnium and Zr.
YOO teaches a device, wherein the first oxide layer comprises ZrO2 (the first oxide layer can be 135a which is ZrO, see fig 3, para 42), and the second oxide layer comprises alternating oxides of the hafnium and Zr (the second layer can be 125a, 135b, 125b, 135c and 125c which comprises alternating layers of HfO and ZnO, see fig 3, para 42).
HSU and YOO are analogous art because they both are directed towards FET devices with FE layers and one of ordinary skill in the art would have had a reasonable expectation of success to modify the device of HSU with the FE material layers of YOO because they are from the same field of endeavor.
It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to modify the device of HSU with the FE material layers of YOO in order to control ferroelectric properties (see YOO para 35).
Regarding claim 13, HSU discloses the electronic device of claim 1.
HSU fails to explicitly disclose a device, wherein the second oxide layer comprises alternating oxides of the hafnium and the second component, and
wherein a surface of the second oxide layer is terminated with an oxide of one of the oxide or the second component.
YOO teaches a device, wherein the second oxide layer comprises alternating oxides of the hafnium and the second component (second oxide layer 40b, 40c and 135d comprises alternating layers of HfO 125 and ZrO 135, see fig 1, para 23), and
wherein a surface of the second oxide layer is terminated with an oxide of one of the oxide or the second component (the top layer is 135c which can be ZrO.
HSU and YOO are analogous art because they both are directed towards FET devices with FE layers and one of ordinary skill in the art would have had a reasonable expectation of success to modify the device of HSU with the FE material layers of YOO because they are from the same field of endeavor.
It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to modify the device of HSU with the FE material layers of YOO in order to control ferroelectric properties (see YOO para 35).
Claim(s) 17-18 is/are rejected under 35 U.S.C. 103 as being unpatentable over HSU (US 20200105897) in view of HEO (US 20210359101).
Regarding claim 17, HSU discloses the electronic device of claim 16.
HSU fails to explicitly disclose a device, wherein
the electronic device is at least one of a fin field-effect transistor (FinFET), a gate-all-around FET (GAAFET), or a multi-bridge channel FET (MBCFET),
the electronic device further comprises a substrate, and
the channel comprises a plurality of channel elements extending in a first direction and are least one of spaced apart from a top surface of the substrate or arranged at intervals from each other in a second direction different from the first direction.
HEO teaches a device, wherein
the electronic device is at least one of a fin field-effect transistor (FinFET), a gate-all-around FET (GAAFET) (the device can be a gate-all-around FET, see fig 10, para 65), or a multi-bridge channel FET (MBCFET),
the electronic device further comprises a substrate (substrate 101, see fig 10, para 49), and
the channel comprises a plurality of channel elements extending in a first direction and are least one of spaced apart from a top surface of the substrate (the device has a plurality of channels 111 which are spaced apart from a top surface of 101, see fig 10, para 65) or arranged at intervals from each other in a second direction different from the first direction.
HSU and HEO are analogous art because they both are directed towards FET devices with FE layers and one of ordinary skill in the art would have had a reasonable expectation of success to modify the device of HSU with the channel structure of HEO because they are from the same field of endeavor.
It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to modify the device of HSU with the channel structure of HEO in order to make a device with improved hysteresis characteristics (see HEO para 7).
Regarding claim 18, HSU and HEO disclose the electronic device of claim 17.
HSU fails to explicitly disclose a device, wherein the ferroelectric layer is one of a plurality of the ferroelectric layers respectively surrounding the plurality of channel elements, and
the gate electrode protrudes from the top surface of the substrate to surround the plurality of the ferroelectric layers.
HEO teaches a device, wherein the ferroelectric layer is one of a plurality of the ferroelectric layers respectively surrounding the plurality of channel elements (there are a plurality of FE layers comprising 210, 220 and 230 each around a channel 111, see fig 10B, para 52), and
the gate electrode protrudes from the top surface of the substrate to surround the plurality of the ferroelectric layers (gate electrode 300 protrudes form 101 to surround 111, see fig 10A, para 46).
HSU and HEO are analogous art because they both are directed towards FET devices with FE layers and one of ordinary skill in the art would have had a reasonable expectation of success to modify the device of HSU with the channel structure of HEO because they are from the same field of endeavor.
It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to modify the device of HSU with the channel structure of HEO in order to make a device with improved hysteresis characteristics (see HEO para 7).
Claim(s) 19 is/are rejected under 35 U.S.C. 103 as being unpatentable over HSU (US 20200105897) in view of INO (US 20190296122).
Regarding claim 19, HSU discloses the electronic device of claim 16.
HSU fails to explicitly disclose a device, comprising a stacked structure in which a plurality of insulating layers and a plurality of the gate electrodes are alternately stacked,
wherein the electronic device further comprises a plurality of channel holes vertically penetrating the stacked structure,
wherein the ferroelectric layer and the conductive material layer are concentrically arranged in each of the plurality of channel holes.
INO teaches a device, comprising a stacked structure in which a plurality of insulating layers and a plurality of the gate electrodes are alternately stacked (the insulating layers 12 and the gates WL are alternately stacked, see fig 7, 50, para 99),
wherein the electronic device further comprises a plurality of channel holes vertically penetrating the stacked structure (the holes for each memory string MS in fig 6, each of which is a hole containing 10 and 16, see fig 7, para 99),
wherein the ferroelectric layer and the conductive material layer are concentrically arranged in each of the plurality of channel holes (10 and 61-63 are concentrically arranged around 16, see fig 7, para 99).
HSU and INO are analogous art because they both are directed towards FET devices with FE layers and one of ordinary skill in the art would have had a reasonable expectation of success to modify the device of HSU with the channel geometry of INO because they are from the same field of endeavor.
It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to modify the device of HSU with the channel geometry of INO in order to increase the memory capacity (see INO para 175).
Conclusion
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/JONAS T BEARDSLEY/Examiner, Art Unit 2811
/SAMUEL A GEBREMARIAM/Primary Examiner, Art Unit 2811