DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claim(s) 1-16 and 20 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by YOO (US 20180240804).
Regarding claim 1, YOO discloses an electronic device comprising:
a conductive material layer (the substrate 101 which includes the transistor channel between the s/d, see fig 4, para 18);
a ferroelectric layer (the superlattice layer 40 is ferroelectric, see fig 4, para 5 and 46) covering the conductive material layer (40 covers at least a portion of the channel region of 101, see fig 4) and having ferroelectric or antiferroelectric properties (see para 5); and
an electrode layer (fig 4, 155, para 18) covering the ferroelectric layer,
wherein the ferroelectric layer comprises a first oxide layer comprising a first component and having a first thickness (40 comprises layer 135d, which can be ZnO which comprises first component Zn and 5 ANG thick, see fig 4, para 46, 49 and 26), and
a second oxide layer comprising hafnium and a second component and having a second thickness that is twice or more the first thickness (40 comprises 40b and 40c which comprise 125b and 125c which can be HfO and 135b and 135c which can be ZnO which comprises the second component Zn, each of which can have a thickness of 5 ANG giving the layer 40b+40c a total thickness of 2 nm, see fig 4, para 26); and
wherein, in the ferroelectric layer, a composition ratio between a sum of the first component and the second component to the hafnium is greater than 1 (the ferroelectric layer 40 has more ZnO layers 135a-d than HfO layers 125a-c, each of which can have the same thickness, see para 28, which means there will be more Zn than Hf in 40).
Regarding claim 2, YOO discloses the electronic device of claim 1, wherein a ratio of the second thickness to the first thickness is 2:1 to 10:1 (the first thickness of 135d can be 5 ANG, and the second thickness of 125c+135c+125b+135b can be 2 nm, giving a thickness ration of 4:1, see para 26).
Regarding claim 3, YOO discloses the electronic device of claim 1, wherein the first thickness is 1 nm or less, and a total thickness of the ferroelectric layer is 3 nm or less (the first thickness of 135d can be 5 ANG, and the second thickness of 125c+135c+125b+135b can be 2 nm, see para 26).
Regarding claim 4, YOO discloses the electronic device of claim 3, wherein the first thickness is 0.2 nm to 1 nm, and the total thickness of the ferroelectric layer is 0.5 nm to 3 nm (the first thickness of 135d can be 5 ANG, and the second thickness of 125c+135c+125b+135b can be 2 nm, giving a total thickness of 2.5nm see para 26).
Regarding claim 5, YOO discloses the electronic device of claim 1, wherein a proportion of the second component is greater than a proportion of the hafnium at a surface of the second oxide layer (the lower surface of the second oxide layer is the lower surface of 135b which is a ZnO layer, and not an HfO layer, see fig 4, para 26).
Regarding claim 6, YOO discloses the electronic device of claim 5, wherein the proportion of the second component is greater than the proportion of the hafnium in a region of the second oxide layer from the surface to a thickness portion of 1/3 or less (the bottom quarter of the second oxide layer 40b+40c is ZnO which will have more Zn than Hf, see fig 4, para 26).
Regarding claim 7, YOO discloses the electronic device of claim 5, wherein
the first component and the second component are Zr (the first oxide layer 135d is ZnO which comprises Zn as a first component and the second oxide layer 40b+c comprises 135b and 135c which comprise Zn as a second component, see fig 4, para 26 and 46),
the first oxide layer comprises ZrO2 (135d can be ZnO, see para 46), and
the second oxide layer comprises alternating oxides of Hf and Zr (40b+c comprise alternating layers of ZnO 135b+c and HfO 125b+c, see fig 4, para 26).
Regarding claim 8, YOO discloses the electronic device of claim 1, wherein the second oxide layer comprises alternating oxides of Hf and the second component (40b+c comprise alternating layers of ZnO 135b+c and HfO 125b+c, see fig 4, para 26), and
a proportion of the second component is greater than a proportion of the hafnium at a surface of the second oxide layer (the bottom surface of the second oxide layer 40b+c is the bottom surface of 135b which is a ZnO layer, which will thus have more Zn than Hf, see fig 4, para 26).
Regarding claim 9, YOO discloses the electronic device of claim 8, wherein the second oxide layer is formed by alternately and repeatedly depositing the oxide of the hafnium and the oxide of the second component in one cycle or in multiple cycles (the superlattice can be formed by alternating depositions, see fig 7-8, para 56-60).
Additionally, “the second oxide layer is formed by alternately and repeatedly depositing the oxide of the hafnium and the oxide of the second component in one cycle or in multiple cycles“ is considered a product-by-process claim. “[E]ven though product-by process claims are limited by and defined by the process, determination of patentability is based on the product itself. The patentability of a product does not depend on its method of production. If the product in the product-by-process claim is the same as or obvious from a product of the prior art, the claim is unpatentable even though the prior product was made by a different process.” In re Thorpe, 777 F.2d 695, 698, 227 USPQ 964, 966 (Fed. Cir. 1985).
Regarding claim 10, YOO discloses the electronic device of claim 1, wherein the first component and the second component are each at least one of Zr (135b-d can be ZnO which contains Zn, see fig 4, para 24 and 46), Si, Al, Y, La, Gd, or Sr.
Regarding claim 11, YOO discloses the electronic device of claim 10, wherein the first component and the second component are the same (135b-d can be ZnO which contains Zn, see fig 4, para 24 and 46), and a composition ratio of an oxide of the first component to an oxide of the hafnium is greater than 1 in the ferroelectric layer (all the layers 125b, 125c, 135b, 135c and 135d can be 5 ANG thick, 125b+c are HfO and 135b+c+d are ZnO, so there will be more Zn than Hf, see fig 4, para 26 and 46).
Regarding claim 12, YOO discloses the electronic device of claim 11, wherein the first oxide layer comprises ZrO2 (135d is ZrO which can be ZrO2, see fig 4, para 15 and 26), and the second oxide layer comprises alternating oxides of the hafnium and Zr (125b-c can be HfO and 135b-c can be ZrO, and 125 and 135 alternate, see fig 4).
Regarding claim 13, YOO discloses the electronic device of claim 1, wherein the second oxide layer comprises alternating oxides of the hafnium and the second component (125b-c can be HfO and 135b-c can be ZrO, and 125 and 135 alternate, see fig 4), and
wherein a surface of the second oxide layer is terminated with an oxide of one of the oxide or the second component (the lower surface of the second oxide layer is the lower surface of 135b which is a ZnO layer, and not an HfO layer, see fig 4, para 26).
Regarding claim 14, YOO discloses the electronic device of claim 1, wherein layers are stacked in an order of the first oxide layer, the second oxide layer, and the electrode layer, or an order of the second oxide layer, the first oxide layer, and the electrode layer (the second oxide layer 40b+c is below the first oxide layer 135d which is below 155, see fig 4), and
ferroelectric crystallization of the ferroelectric layer is a result of heat treatment performed before and/or after the electrode layer is formed (the layers can be heat treated to crystallize them, see para 64).
Additionally, “ferroelectric crystallization of the ferroelectric layer is a result of heat treatment performed before and/or after the electrode layer is formed” is considered a product-by-process claim. “[E]ven though product-by process claims are limited by and defined by the process, determination of patentability is based on the product itself. The patentability of a product does not depend on its method of production. If the product in the product-by-process claim is the same as or obvious from a product of the prior art, the claim is unpatentable even though the prior product was made by a different process.” In re Thorpe, 777 F.2d 695, 698, 227 USPQ 964, 966 (Fed. Cir. 1985).
Regarding claim 15, YOO discloses the electronic device of claim 1, further comprising: a dielectric layer, that is not ferroelectric, between at least one of the conductive material layer and the ferroelectric layer or the ferroelectric layer and the electrode layer (115 is between 101 and 40, see fig 4, para 21).
Regarding claim 16, YOO discloses the electronic device of claim 1, wherein the conductive material layer comprises a channel (101 comprises a channel between 102 and 103, see fig 4, para 33), the electrode layer comprises a gate electrode (155 can be a gate electrode, see fig 4, para 18), and the electronic device is at least one of a logic or memory device (the device can be a memory device, see para 18).
Regarding claim 20, YOO discloses an electronic apparatus comprising
at least one electronic device (the memory device 4, see fig 4, para 45), the at least one electronic device comprises:
a conductive material layer (the substrate 101 which includes the transistor channel between the s/d, see fig 4, para 18);
a ferroelectric layer (the superlattice layer 40 is ferroelectric, see fig 4, para 5 and 46) covering the conductive material layer (40 covers at least a portion of the channel region of 101, see fig 4) and having ferroelectric or antiferroelectric properties (see para 5); and
an electrode layer (fig 4, 155, para 18) covering the ferroelectric layer,
wherein the ferroelectric layer comprises a first oxide layer comprising a first component (40 comprises layer 135d, which can be ZnO which comprises first component Zn and 5 ANG thick, see fig 4, para 46, 49 and 26), and
a second oxide layer comprising hafnium and a second component (40 comprises 40b and 40c which comprise 125b and 125c which can be HfO and 135b and 135c which can be ZnO which comprises the second component Zn, each of which can have a thickness of 5 ANG giving the layer 40b+40c a total thickness of 2 nm, see fig 4, para 26); and
wherein, in the ferroelectric layer, a composition ratio between a sum of the first component and the second component to the hafnium is greater than 1 (the ferroelectric layer 40 has more ZnO layers 135a-d than HfO layers 125a-c, each of which can have the same thickness, see para 28, which means there will be more Zn than Hf in 40).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 17-18 is/are rejected under 35 U.S.C. 103 as being unpatentable over YOO (US 20180240804) in view of HEO (US 20210359101).
Regarding claim 17, YOO discloses the electronic device of claim 16.
YOO fails to explicitly disclose a device, wherein
the electronic device is at least one of a fin field-effect transistor (FinFET), a gate-all-around FET (GAAFET), or a multi-bridge channel FET (MBCFET),
the electronic device further comprises a substrate, and
the channel comprises a plurality of channel elements extending in a first direction and are least one of spaced apart from a top surface of the substrate or arranged at intervals from each other in a second direction different from the first direction.
HEO teaches a device, wherein
the electronic device is at least one of a fin field-effect transistor (FinFET), a gate-all-around FET (GAAFET) (the device can be a gate-all-around FET, see fig 10, para 65), or a multi-bridge channel FET (MBCFET),
the electronic device further comprises a substrate (substrate 101, see fig 10, para 49), and
the channel comprises a plurality of channel elements extending in a first direction and are least one of spaced apart from a top surface of the substrate (the device has a plurality of channels 111 which are spaced apart from a top surface of 101, see fig 10, para 65) or arranged at intervals from each other in a second direction different from the first direction.
YOO and HEO are analogous art because they both are directed towards semiconductor devices and one of ordinary skill in the art would have had a reasonable expectation of success to modify the device of YOO with the gate-all-around structure of HEO because they are from the same field of endeavor.
It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to modify the device of YOO with the gate-all-around structure of HEO in order to make a device with improved hysteresis characteristics (see HEO para 7).
Regarding claim 18, YOO and HEO disclose the electronic device of claim 17.
YOO fails to explicitly disclose a device, wherein the ferroelectric layer is one of a plurality of the ferroelectric layers respectively surrounding the plurality of channel elements, and
the gate electrode protrudes from the top surface of the substrate to surround the plurality of the ferroelectric layers.
HEO teaches a device, wherein the ferroelectric layer is one of a plurality of the ferroelectric layers respectively surrounding the plurality of channel elements (there are a plurality of FE layers comprising 210, 220 and 230 each around a channel 111, see fig 10B, para 52), and
the gate electrode protrudes from the top surface of the substrate to surround the plurality of the ferroelectric layers (gate electrode 300 protrudes form 101 to surround 111, see fig 10A, para 46).
YOO and HEO are analogous art because they both are directed towards semiconductor devices and one of ordinary skill in the art would have had a reasonable expectation of success to modify the device of YOO with the gate-all-around structure of HEO because they are from the same field of endeavor.
It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to modify the device of YOO with the gate-all-around structure of HEO in order to make a device with improved hysteresis characteristics (see HEO para 7).
Claim(s) 19 is/are rejected under 35 U.S.C. 103 as being unpatentable over YOO (US 20180240804) in view of INO (US 20190296122).
Regarding claim 19, YOO discloses the electronic device of claim 16.
YOO fails to explicitly disclose a device, comprising a stacked structure in which a plurality of insulating layers and a plurality of the gate electrodes are alternately stacked,
wherein the electronic device further comprises a plurality of channel holes vertically penetrating the stacked structure,
wherein the ferroelectric layer and the conductive material layer are concentrically arranged in each of the plurality of channel holes.
INO teaches a device, comprising a stacked structure in which a plurality of insulating layers and a plurality of the gate electrodes are alternately stacked (the insulating layers 12 and the gates WL are alternately stacked, see fig 7, 50, para 99),
wherein the electronic device further comprises a plurality of channel holes vertically penetrating the stacked structure (the holes for each memory string MS in fig 6, each of which is a hole containing 10 and 16, see fig 7, para 99),
wherein the ferroelectric layer and the conductive material layer are concentrically arranged in each of the plurality of channel holes (10 and 61-63 are concentrically arranged around 16, see fig 7, para 99).
YOO and INO are analogous art because they both are directed towards semiconductor transistor devices and one of ordinary skill in the art would have had a reasonable expectation of success to modify the device of YOO with the stacked structure of INO because they are from the same field of endeavor.
It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to modify the device of YOO with the stacked structure of INO in order to increase the memory capacity (see INO para 175).
Response to Arguments
Applicant's arguments filed 5/18/2026 have been fully considered but they are not persuasive.
The applicant argues that YOO does not overcome the deficiencies of HSU to teach at least claim 1. No specific reason for this is given. This argument is unpersuasive, since YOO discloses a device with a ferroelectric layer comprising alternating layers of HfO and ZnO (40a-c, which each comprise a ZnO layer 135 and an HfO layer 125, see YOO fig 4, para 46) and an additional layer of ZnO (135d, see fig 4, para 46), and each of the layers has the same thickness, therefore there will be more Zn than Hf in 40. Additionally, the applicant appears to be arguing that the two oxide layers which comprise the ferroelectric layer must collectively make up the entire ferroelectric layer, which is not true. The word “comprising” does not imply that the two oxide layers make up the entire ferroelectric layer. For at least these reasons, and those given in the rejection above, YOO discloses every element of claim 1, which is not patentable over YOO.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to JONAS TYLER BEARDSLEY whose telephone number is (571)272-3227. The examiner can normally be reached 930-600 M-F.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Lynne Gurley can be reached at 571-272-1670. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/JONAS T BEARDSLEY/Examiner, Art Unit 2811
/SAMUEL A GEBREMARIAM/Primary Examiner, Art Unit 2811
Prosecution Insights