Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Amendments
Acknowledgment is made of the amendment filed 06/05/2026, in which: claims 1 and 3 are amended; claim 2 is cancelled; and the rejection of the claims are traversed. Claims 1 and 3-6 are currently pending an Office action on the merits as follows.
Response to Arguments
Applicant’s arguments, filed 06/05/2026, with respect to the rejection(s) of claim(s) 1 and 3-6 under 35 U.S.C. 103 have been fully considered and are persuasive. Therefore, the rejection has been withdrawn. However, upon further consideration, a new ground(s) of rejection is made in view of Xu et al, US 20210193013.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claim(s) 1 and 3 is/are rejected under 35 U.S.C. 102(a)(1)/(a)(2) as being anticipated by Xu et al, US 20210193013.
Regarding claim 1, Xu discloses : A thin film transistor array substrate, comprising: a substrate including an active area and a non-active area disposed in the vicinity of the active area(First and second region on substrate [0022-0024]); and a plurality of pixels disposed in the active area(subpixel region on substrate [0007]), wherein each pixel includes a plurality of sub pixels(Subpixel region to include subpixels [0008]), and each sub pixel includes a driving thin film transistor including an oxide semiconductor pattern(semiconductor layer may include oxide [0077]), and the driving thin film transistor in the pixel includes sub pixels having different ratios of a width to a length of a channel of the driving thin film transistor(Driving transistors channel region of different colors have different width to length ratios [0009]), and wherein the plurality of sub pixels include red, green, and blue sub pixels, and a ratio of a width to a length of a channel of the driving thin film transistor included in the blue sub pixel is smallest(In an embodiment a first color is red, a second color is green and a third color is blue, where the blue subpixel is the smallest [0009, 0015]).
Regarding claim 3, Xu discloses : The thin film transistor array substrate according to claim 1,wherein the length of the channel of the driving thin film transistor included in the blue sub pixel among the pixel is largest(Length of blue subpixel is longest [0012]).
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 4 is/are rejected under 35 U.S.C. 103 as being unpatentable over Xu et al, US 20210193013 in view of Jo et al, US 20210202631.
Regarding claim 4, Xu discloses : The thin film transistor array substrate according to claim 1.
Xu does not disclose : wherein the driving thin film transistor includes: a first oxide semiconductor pattern disposed on the substrate; a first gate electrode which overlaps a part of the first oxide semiconductor pattern; a first lower conductive pattern overlapping a part of the first oxide semiconductor pattern and disposed below the first oxide semiconductor pattern; and a first source electrode and a first drain electrode which are electrically connected to the first oxide semiconductor pattern, and any one of the first source electrode and the first drain electrode is electrically connected to the first lower conductive pattern.
However, in the same field of endeavor, Jo teaches : wherein the driving thin film transistor includes: a first oxide semiconductor pattern disposed on the substrate(Fig. 4a, #da2 disposed on #sub); a first gate electrode which overlaps a part of the first oxide semiconductor pattern(#ge2); a first lower conductive pattern overlapping a part of the first oxide semiconductor pattern and disposed below the first oxide semiconductor pattern(#ls); and a first source electrode and a first drain electrode which are electrically connected to the first oxide semiconductor pattern(#dt to include source and drain electrode [0067]), and any one of the first source electrode and the first drain electrode is electrically connected to the first lower conductive pattern(#de2 may be connected to #ls [0088]).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date to apply the teachings of Jo to Xu to include a lower conductive pattern connected to a drain electrode to protect and oxide semiconductor from external light (Jo [0118]).
Claim(s) 5 and 6 is/are rejected under 35 U.S.C. 103 as being unpatentable over Xu et al, US 20210193013 in view of Jo et al, US 20210202631 in further view of Koo et al, US 20180175077.
Regarding claim 5, Xu as modified by Jo discloses : The thin film transistor array substrate according to claim 4.
Xu as modified by Jo does not disclose : wherein a parasitic capacitance generated between the first oxide semiconductor pattern and the first gate electrode is smaller than a parasitic capacitance generated between the first oxide semiconductor pattern and the first lower conductive pattern.
However, in the same field of endeavor, Koo teaches : wherein a parasitic capacitance generated between the first oxide semiconductor pattern and the first gate electrode is smaller than a parasitic capacitance generated between the first oxide semiconductor pattern and the first lower conductive pattern(Fig. 10, S-factor of driving transistor where in the capacitance is engineered according to the relationship C = kA/d teaching that a capacitance between and electrode and an active layer is modified by area, dielectric material, or separation [0145-0146]).
It would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to modify the parasitic capacitance between a gate electrode and active layer to be smaller than a parasitic capacitance between and active layer and a lower conductive pattern, since it has been held that discovering an optimum value of a result effective variable involves only routine skill in the art. See KSR International Co. v. Teleflex Inc., 82 USPQ2d 1385 (2007).
Regarding claim 6, Xu as modified by Jo and Koo discloses : The thin film transistor array substrate according to claim 5.
Jo teaches : further comprising: a light emitting diode part including: an anode electrode which is connected to the driving thin film transistor(Fig. 4a, #AE connected to #DE2); a cathode electrode corresponding to the anode electrode(#CE); and a light emitting layer disposed between the anode electrode and the cathode electrode(#EML).
Conclusion
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/D.T./ Examiner, Art Unit 2897 /CHAD M DICKE/Supervisory Patent Examiner, Art Unit 2897
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