Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim 1 is/are rejected under 35 U.S.C. 103 as being unpatentable over Lee et al, US 20230247863, hereafter ‘Lee’ in view of Mou et al, US 20220044636, hereafter ‘Mou’.
Regarding claim 1, Lee discloses : A thin film transistor array substrate, comprising: a substrate including an active area and a non-active area disposed in the vicinity of the active area(Fig. 1, #1 to include #DA and #BR and #SR [0081]); and a plurality of pixels disposed in the active area(#PX disposed in #DA), wherein each pixel includes a plurality of sub pixels(#PX may emit red, green, or blue light [0090]), and each sub pixel includes a driving thin film transistor including an oxide semiconductor pattern(#T1-T7 may include a semiconducting layer including oxide [0162-0163]).
Lee does not disclose : the driving thin film transistor in the pixel includes sub pixels having different ratios of a width to a length of a channel of the driving thin film transistor.
However, in the same field of endeavor, Mou teaches : the driving thin film transistor in the pixel includes sub pixels having different ratios of a width to a length of a channel of the driving thin film transistor(transistors may be oxide semiconductor thin film transistors [0158] where the modification of a channel’s width and length ratio affects channel mobility, channel capacitance, current, voltage between gate electrode and source electrode, and threshold voltage of a driving transistor of each subpixel [0069-0080]).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to adjust a width and length ratio of a subpixel’s driving transistor channel with routine experiment and optimization. In re Woodruff, 16 USPQ2d 1935, 1937 (Fed. Cir. 1990).
Claims 2 and 3 is/are rejected under 35 U.S.C. 103 as being unpatentable over Lee et al, US 20230247863, hereafter ‘Lee’ in view of Mou et al, US 20220044636, hereafter ‘Mou’, in further view of Yamanaka, US 20210264854, hereafter ‘Yamanaka’.
Regarding claim 2, Lee as modified by Mou discloses : The thin film transistor array substrate according to claim 1.
Lee as modified by Mou does not disclose : wherein the plurality of sub pixels includes red, green, and blue sub pixels, and a ratio of a width to a length of a channel of the driving thin film transistor included in the blue sub pixel is smallest.
However, in the same field of endeavor, Yamanaka teaches : wherein the plurality of sub pixels includes red, green, and blue sub pixels, and a ratio of a width to a length of a channel of the driving thin film transistor included in the blue sub pixel is smallest(Blue subpixel’s driving transistor has a channel length shorter than a channel length of red and green [0079]).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date to apply the teachings of Yamanaka to Lee and Mou to modify a channel’s length and width ratio of a transistor to improve display quality from degradation in transistors [0006]).
Regarding claim 3, Lee as modified by Mou and discloses : The thin film transistor array substrate according to claim 2.
Mou teaches : wherein the length of the channel of the driving thin film transistor included in the blue sub pixel among the pixel is largest(Channel width-length ratio of red, green and blue may be 1:(0.7-1.3):(1.5-2.5) [0059]).
Claim 4 is/are rejected under 35 U.S.C. 103 as being unpatentable over Lee et al, US 20230247863, hereafter ‘Lee’ in view of Mou et al, US 20220044636, hereafter ‘Mou’ in further view of Jo et al, US 20210202631, hereafter ‘Jo’.
Regarding claim 4, Lee as modified by Mou discloses : The thin film transistor array substrate according to claim 1.
Lee teaches : wherein the driving thin film transistor includes a first oxide semiconductor pattern disposed on the substrate(Fig. 14, #1101); a first gate electrode which overlaps a part of the first oxide semiconductor pattern(#1221 overlaps #1101 [0192]); and a first source electrode and a first drain electrode which are electrically connected to the first oxide semiconductor pattern(#1101s and #1101d [0204]).
Lee as modified by Mou does not disclose : a first lower conductive pattern overlapping a part of the first oxide semiconductor pattern and disposed below the first oxide semiconductor pattern; and any one of the first source electrode and the first drain electrode is electrically connected to the first lower conductive pattern.
However, in the same field of endeavor, Jo teaches : a first lower conductive pattern overlapping a part of the first oxide semiconductor pattern and disposed below the first oxide semiconductor pattern(Fig. 4a, #LS disposed in #BUF); and any one of the first source electrode and the first drain electrode is electrically connected to the first lower conductive pattern(#LS may be connected to DE2 [0088]).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date to apply the teachings of Jo to Lee and Mou to include a lower conductive pattern connected to a drain electrode to protect an oxide semiconductor device from external light (Jo, [0118]).
Claims 5 and 6 is/are rejected under 35 U.S.C. 103 as being unpatentable over Lee et al, US 20230247863, hereafter ‘Lee’ in view of Mou et al, US 20220044636, hereafter ‘Mou’ in further view of Jo et al, US 20210202631, hereafter ‘Jo’, in further view of Lin et al, US 20160254338, hereafter ‘Lin’.
Regarding claim 5, Lee as modified by Mou and Jo discloses : The thin film transistor array substrate according to claim 4.
Lee as modified by Mou and Jo does not disclose : wherein a parasitic capacitance generated between the first oxide semiconductor pattern and the first gate electrode is smaller than a parasitic capacitance generated between the first oxide semiconductor pattern and the first lower conductive pattern.
However, in the same field of endeavor, Lin teaches : wherein a parasitic capacitance generated between the first oxide semiconductor pattern and the first gate electrode is smaller than a parasitic capacitance generated between the first oxide semiconductor pattern and the first lower conductive pattern(#250 may be formed below drive transistors to reduce parasitic capacitance within pixels [0051] and may be shorted to ground which increases capacitance [0057]).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date to apply the teachings of Lin to Lee, Mou, and Jo to provide a lower conductive pattern below a semiconductor pattern to minimize dynamic power consumption in displays (Lin, [0051]).
Regarding claim 6, Lee as modified by Mou, Jo, and Lin discloses : The thin film transistor array substrate according to claim 5.
Jo teaches : further comprising: a light emitting diode part including: an anode electrode which is connected to the driving thin film transistor(Fig. 4a, #AE connected to #DE2 of a driving transistor) ; a cathode electrode corresponding to the anode electrode(#CE); and a light emitting layer disposed between the anode electrode and the cathode electrode(#EML).
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure : US 20170278874– Width and length ratio channel modifications in display devices.
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/D.T./Examiner, Art Unit 2897 /CHAD M DICKE/Supervisory Patent Examiner, Art Unit 2897