Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
DETAILED ACTION
This office action is in response to the filing of the Applicant Arguments/Remarks Made in an Amendment on 07/27/2026. Currently, claims 1-18 are pending in the application. Claims 11-18 are withdrawn from Consideration.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102 of this title, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-4 and 6-10 are rejected under 35 U.S.C. 103 as being obvious over Nakata (US 20170092747 A1) in view of CHANG et al (US 20150236109 A1).
Regarding claim 1, Figures 2-4 of Nakata disclose a fabrication method of a semiconductor device, comprising:
forming a semiconductor stack (13-15, [0025]) on a substrate (11, [0025]);
forming a N type doping layer (26, [0029]), on the semiconductor stack (13-15, [0025]);
patterning (in Figure 3A-3B, [0030]) the N type doping layer (26) to form a source N type doping part (16a, [0031]) and a drain N type doping part (16b, [0031]);
forming a source electrode (31, Figure 4, [0031]) on the source N type doping part (16a);
forming a drain electrode (32, Figure 4, [0031]) on the drain N type doping part (16b); and
forming a gate electrode (33, Figure 4, [0043]) that is located between the source N type doping part (16a) and the drain N type doping part (16b) on the semiconductor stack (13-15).
Nakata does not teach that the patterning of the N type doping layer (26) by electron beam lithography.
However, CHANG is a pertinent art which teaches a method of forming a HEMT device ([0005]), wherein CHANG teaches of using an electron beam lithography in patterning the source/drain region and forming a gate in between the source/drain region ([0006] and [0011]).
Thus, it would have been obvious to one of the ordinary skill in the art before the effective filing date of the claimed invention to use a step of patterning the N type doping layer (26, Figure 3A-3B, Nakata) by electron beam lithography in the method of making the device of Nakata according to the teaching of CHANG in order to shape the source and drain regions (16a/16b) and to form the gate (33) in between the source/drain region with precise dimension ([0029] of CHANG) instead of dry etching ([0030] of Nakata). Further, the court has held that a simple substitution of one known element for another (electron beam lithography instead of dry etching) to obtain predictable results is obvious. KSR Int'l v. Teleflex Inc., 127 S.Ct. 1727 (2007).
Regarding claim 2, Figures 2-4 of Nakata disclose that the fabrication method of a semiconductor device according to claim 1, wherein the semiconductor stack (13-15, [0025]) comprises a buffer layer (13), a channel layer (14), a barrier layer (15) and a cap layer (not shown, [0053]) that are sequentially stacked, and the channel layer (14) is in contact with the barrier layer (15) on a heterojunction (formed due to variation in bandgap in different material).
Regarding claim 3, Figures 2-4 of Nakata disclose that the fabrication method of a semiconductor device according to claim 2, wherein the channel layer (14, [0025]) and the cap layer ([0053]) comprises gallium nitride, and the barrier layer ([0036]) comprises at least one of AlN, AlGaN and InAlN.
Regarding claim 4, Figures 2-4 of Nakata disclose that the fabrication method of a semiconductor device according to claim 2, wherein forming the N type doping layer (26) on the semiconductor stack comprises: forming at least one source cavity (61 at 61a, [0027]) and at least one drain cavity (61 at 61a, [0027]) in the semiconductor stack, wherein the at least one source cavity and the at least one drain cavity penetrate through the barrier layer (15) and the cap layer without penetrating through the channel layer (14); and forming the N type doping layer in the at least one source cavity, in the at least one drain cavity and on the cap layer ([0053]).
Regarding claim 6, Figures 2-4 of Nakata disclose that the fabrication method of a semiconductor device according to claim 1, further comprising: forming a protective layer (41, [0019]) on the source N type doping part (16a), the drain N type doping part (16b) and the semiconductor stack (13-15); wherein, forming the source electrode on the source N type doping part comprises forming the source electrode (31) in a first opening of the protective layer exposing the source N type doping part (16a); wherein, forming the drain electrode (32) on the drain N type doping part (16b) comprises forming the drain electrode in a second opening of the protective layer exposing the drain N type doping part (16b); and wherein, forming the gate electrode (33, [0043]) on the semiconductor stack comprises forming the gate electrode in a third opening of the protective layer (41) exposing the semiconductor stack (13-15).
Regarding claim 7, Figures 2-4 of Nakata do not explicitly teach that the fabrication method of a semiconductor device according to claim 6, wherein the protective layer (41, [0043]) is formed on the source N type doping part (16a), the drain N type doping part (16b) and the semiconductor stack (13-15) by atomic layer deposition. However, the Examiner takes an official notice that such deposition method is very well in pertinent prior arts.
Regarding claim 8, Figures 2-4 of Nakata do not explicitly teach that the fabrication method of a semiconductor device according to claim 6, wherein the third opening of the protective layer (41, [0043]) is formed by atomic layer etching. However, the Examiner takes an official notice that such etching method is very well in pertinent prior arts.
Regarding claim 9, Figures 2-4 of Nakata disclose that the fabrication method of a semiconductor device according to claim 1, wherein the N type doping layer (26) is a N type GaN doping layer ([0017]).
Regarding claim 10, Figures 2-4 of Nakata do not explicitly teach that the fabrication method of a semiconductor device according to claim 1, wherein a gap width between the source N type doping part (16a) and the drain N type doping part (16b) is at least ten times larger than a width of the gate electrode (33).
However, it would have been obvious to one having ordinary skill in the art at the time of the invention was made to use the above claimed ranges in order to form an improved device since it has been held that where the general conditions of a claim are disclosed in the prior art, discovering the optimum or working range involves only routine skill in the art. In re Aller, 105 USPQ 233.
Claim 5 is rejected under 35 U.S.C. 103 as being obvious over Nakata (US 20170092747 A1) in view of CHANG et al (US 20150236109 A1) as applied to claim 4 above, and further in view of YOON et al (KR 20180053207 A). An English translation of YOON is provided with this office action.
Regarding claim 5, Figures 2-4 of Nakata in view of CHNAG do not teach that the fabrication method of a semiconductor device according to claim 4, wherein the at least one source cavity comprises a plurality of source cavities and the at least one drain cavity comprises a plurality of drain cavities.
However, YOON is a pertinent art which teaches a HEMT device, wherein Figures 7-8 of YOON teach that the HEMT device having a source/drain region (210/220) with plurality of plurality of cavity to form electrode with lower resistance and improved electrical characteristics (Background of YOON).
Thus, it would have been obvious to one of the ordinary skill in the art before the effective filing date of the claimed invention to modify the method of Nakata in view of CHANG wherein the at least one source cavity comprises a plurality of source cavities and the at least one drain cavity comprises a plurality of drain cavities for forming a plurality of connections with the source and drain regions (16a/16b, Figure 4 of Nakata) in order to form a high-frequency device manufacturing method with improved electrical characteristics (Background of YOON).
Response to Arguments
Applicant's arguments filed on 07/27/2026 have been fully considered but they are not persuasive.
Applicant’s main arguments regarding claim 1 include: CHANG discloses the feature of patterning the photoresist instead of N type doping layer. The object on which the electron-beam lithography is performed in the present is totally different from the object on which the electron-beam lithography in CHANG. Accordingly, CHANG merely teaches one of ordinary skill in the art to pattern the photoresist by electron-beam lithography, and CHANG fails to teach one of ordinary skill in the art to pattern the N type doping layer by electron-beam lithography.
In response, the Examiner respectfully disagrees and would like to point out that Figures 3A-3B of Nakata teach of patterning the N type doping layer 26 by dry or wet etching using a photoresist layer ([0030] and [0053]) but Nakata does not teach electron-beam lithography which is very well known for etching (patterning) different layers to form recess in semiconductor devices according to CHANG ([0006] and [0011]), wherein Figure 3A-3B of Nakata teach to form a recess between 16a and 16b on top of layer 15. Further, the Examiner would like to point out that Figure 3 of CHANG teaches of forming a recess for gate electrode by removing semiconductor layers (n+ InGaAs Cap layer) as well as removing photoresist (Figure 3 and Claim 3 of CHANG). Thus, electron-beam lithography can be used to pattern layers by etching photoresist layers as well as doped semiconductor layers according to the teaching of CHANG.
Thus, it would have been obvious to one of the ordinary skill in the art before the effective filing date of the claimed invention to use a step of patterning the N type doping layer (26, Figure 3A-3B, Nakata) by electron beam lithography in the method of making the device of Nakata according to the teaching of CHANG in order to shape the source and drain regions (16a/16b) and to form the gate (33) in between the source/drain region with precise dimension ([0029] of CHANG) instead of dry etching ([0030] of Nakata). Further, the court has held that a simple substitution of one known element for another (electron beam lithography instead of dry etching) to obtain predictable results is obvious. KSR Int'l v. Teleflex Inc., 127 S.Ct. 1727 (2007).
Conclusion
THIS ACTION IS MADE FINAL. Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any extension fee pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to KHAJA AHMAD whose telephone number is (571)270-7991. The examiner can normally be reached on Monday to Friday from 8:00 AM to 5:00 PM (Eastern Time).
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, GAUTHIER STEVEN B, can be reached on (571)270-0373. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/KHAJA AHMAD/
Primary Examiner, Art Unit 2813
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