DETAILED ACTION
The examiner has considered Applicant’s arguments and finds them persuasive. Accordingly, the previous rejection is withdrawn as moot in view of the new ground of rejection set forth below.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1, 9 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Wang et al., U.S.Pub. No. 2008/1251938.
Regarding claim 1, Wang discloses a chip packaging method comprising:
preparing a plurality of chip package units, each of the plurality of chip package units having a panel form (substrate 104 panel/array [0059]-[0060]) and including a plurality of dies (array of IC chips, multi-chip in a single IC package [0007], [0060]),
sequentially stacking the plurality of chip package units on a substrate (Fig. 5), and using a thermal compression bonding process ([0060], using a thermoplastic adhesive component 107 for bonding packages together) to electrically connect the plurality of chip package units to each other and electrically connect the plurality of chip package units and the substrate to each other, to obtain a stack (Fig. 5), and
cutting the stack to form single packages ([0061]).
Regarding claim 9, Wang discloses a chip packaging method comprising:
a plurality of chip package units, each of the plurality of chip package units having a panel form (substrate 104 panel/array [0059]-[0060]) and including a plurality of dies (array of IC chips, multi-chip in a single IC package [0007], [0060]),
wherein each chip package comprises:
a carrier,
a plurality of dies on the carrier (Figs. 1-3),
an encapsulation layer, of a molding material, on side surfaces of dies, wherein the plurality of chip package units is electrically connected to each other and connected to the substrate by a thermal compression bonding process ([0060], using a thermoplastic adhesive component 107 for bonding packages together).
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 2-8, 10-12, 14-20 are rejected under 35 U.S.C. 103 as being unpatentable over Wang et al., U.S. Pub. No. 2008/1251938, in view of Bhushan et al., U.S. Pub. No. 2023/0048311 (this reference qualifies as a 102(a)(1) until a certified English translation is submitted of the foreign priority application).
Regarding claim 2, Wang fails to disclose: wherein the preparing of the plurality of chip package units comprises, for each chip package unit from among the plurality of chip package units:
scribing an original wafer to obtain the plurality of dies that correspond to the chip package unit,
but Wang discloses mounting the plurality of dies that correspond to the chip package unit on a carrier, and using a molding material to encapsulate the plurality of dies that are mounted on the carrier, to obtain an encapsulator,
thinning the encapsulator to obtain a preliminary chip package unit, the preliminary chip package unit having the panel form, and
forming an electrical connection component on the preliminary chip package unit.
Bhushan et al. discloses:
wherein the preparing of the plurality of chip package units comprises, for each chip package unit from among the plurality of chip package units:
scribing (line 115) an original wafer to obtain the plurality of dies 110 that correspond to the chip package unit (Fig. 1) [0033],
and same as Wang, Bhushan discloses mounting the plurality of dies that correspond to the chip package unit on a carrier [0003], [0033], and using a molding material to encapsulate the plurality of dies that are mounted on the carrier, to obtain an encapsulator,
thinning the encapsulator to obtain a preliminary chip package unit, the preliminary chip package unit having the panel form ([0016], removing the excess encapsulating material), and
forming an electrical connection component on the preliminary chip package unit ([0003], [0018], forming interconnects).
It would have been obvious to one having ordinary skill in the art at the time the invention was made to apply the method of Bhushan in Wang’s in order to facilitate cutting the wafer into individual dies accurately and efficiently, also to protect the die and delicate wire bonds from damage and contaminant, improve durability during handling, shipping, and board assembly, help reduce stress during temperature cycling, prevent short circuits, expose the metal for proper soldering, remove resin covering the contacts, eliminate unwanted material bridging conductor, enable individual package separation, and to provide interconnection links from the die to the outside.
Regarding claim 3, Bhushan et al. discloses wherein the electrical connection component includes through silicon vias and contact pads (Figs. 2A-2C, 3; [0029], [0034]).
Regarding claim 4, Both Wang and Bhushan et al. disclose wherein the carrier includes a non-conductive film or a non-conductive paste as an under-fill material (Li: abstract; Bhushan: [0025]).
Regarding claim 5, Bhushan discloses each of plurality of chip package is configured as a substrate structure formed of the plurality of dies, the molding materials, and the non-conductive film (Fig. 3) and wherein the substrate structure has the panel form (flat form).
Regarding claim 6, it is well known in the art that the substrate can act as barrier layer in the thermal compression bonding process because the substrate has lower thermal conductivity and acts as insulating material.
Regarding claim 7, Bhushan discloses wherein thinning the encapsulator comprising partially removing the molding material to expose top surface of the die, remaining portions of the molding material are provided on side surface of each of the dies.
Regarding claim 8, Bhushan discloses wherein the thinning of the encapsulator comprises partially removing the molding material such that the molding material remains on top surface of the plurality of dies ([0016], removing the excess encapsulating material, Fig. 3).
Regarding claim 10, Wang fails to disclose the dies are configured to be thinned (after undergoing a scribing process, a mounting process, and an encapsulating process – which directs to a method and thus not considered). Bhushan et al. discloses the plurality of chip package units are configured to be thinned (Fig. 1a, the molding layer 114). It would have been obvious to one having ordinary skill in the art at the time the invention was made to thin the package (removing excess unwanted mold) in order to expose the metal for proper soldering, remove molding that covering the contacts, eliminate unwanted material bridging conductor, and enable individual package separation.
Regarding claims 11-12, Bhushan et al. discloses wherein the electrical connection component or at least two chip package units includes through silicon vias and contact pads (Figs. 2A-2C, 3; [0029], [0034]). Bhushan et al. discloses wherein the carrier includes a non-conductive film or a non-conductive paste as an under-fill material (Bhushan: [0025]).
Regarding claim 14, Wang et al. discloses a method of preparing a chip package unit comprising:
mounting the plurality of dies that correspond to the chip package unit on a carrier (Fig. 5), and using a molding material 114 to encapsulate the plurality of dies that are mounted on the carrier, to obtain an encapsulator 114 (Fig. 6),
thinning the encapsulator 114 to obtain a preliminary chip package unit, the preliminary chip package unit having the panel form, removing the excess encapsulating material (Figs 1a, 6-8) and
obtaining the chip package unit, the obtaining comprising forming an electrical connection component on the preliminary chip package unit (the wiring; Fig.10).
Wang fails to disclose scribing an original wafer to obtain the plurality of dies that correspond to the chip package unit.
Bhushan et al. discloses:
wherein the preparing of the plurality of chip package units comprises, for each chip package unit from among the plurality of chip package units:
scribing (line 115) an original wafer to obtain the plurality of dies 110 that correspond to the chip package unit (Fig. 1) [0033],
It would have been obvious to one having ordinary skill in the art at the time the invention was made to apply the method of Bhushan in Wang’s in order to facilitate cutting the wafer into individual dies accurately and efficiently, also to protect the die and delicate wire bonds from damage and contaminant, improve durability during handling, shipping, and board assembly.
Regarding claim 15, Wang et al. discloses wherein the electrical connection component includes through silicon vias and contact pads Fig. 3).
Regarding claim 16, Wang fails to disclose wherein the carrier includes a non-conductive film or non-conductive paste as an under-fill material. Bhushan et al. disclose wherein the carrier includes a non-conductive film or a non-conductive paste as an under-fill material [0025]. It would have been obvious to one or ordinary skill in the art at the time of the invention was made to modify Wang in view of Bhushan because the underfill material can improve bonding reliability, support the chips during assembly, reduces void formation, accommodate thermal stress.
Regarding claim 17, Wang et al. discloses each of plurality of chip package is configured as a substrate structure formed of the plurality of dies, the molding materials, and the non-conductive film (Fig. 6-8) and wherein the substrate structure has the panel form (flat form).
Regarding claim 18, it is inherent in the art that the substrate can act as barrier layer in the thermal compression bonding process because the substrate has lower thermal conductivity and acts as insulating material.
Regarding claim 19, Wang et al. discloses wherein thinning the encapsulator comprising partially removing the molding material to expose top surface of the die, remaining portions of the molding material are provided on side surface of each of the dies (Fig. 1a, 6-8).
Regarding claim 20, Wang discloses thinning by removing the molding material. Bhushan discloses wherein the thinning of the encapsulator comprises partially removing the molding material such that the molding material remains on top surface of the plurality of dies, removing the excess encapsulating material, Fig. 1a, figs. 6-7).
Claim 13 is rejected under 35 U.S.C. 103 as being unpatentable over Wang et al., U.S.Pub. No. 2008/1251938, in view of Chiang et al., U.S. Pub. No. 2023/0035212.
Regarding claim 13, Wang fails to disclose wherein an uppermost one of the plurality of chip package units does not include a through silicon via. Chiang discloses the uppermost units does not include a through silicon via (Figs. 3 & 8). It has been obvious to one having ordinary skill in the art at the time the invention was made to not having through silicon via on the uppermost unit in order to avoid unnecessary TSVs to improve yield and reliability because the top package unit is more exposed and faces encapsulation, therefore adding TSV just to weaken structure and increase risk of mechanical failure.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to THAO P LE whose telephone number is (571)272-1785. The examiner can normally be reached on Monday-Friday 9AM-6PM.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Jeff Natalini can be reached on 571-272-2266. The fax phone number for the organization where this application or proceeding is assigned is 703-872-9306.
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/THAO P LE/Primary Examiner, Art Unit 2818
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