Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Election/Restrictions
Applicant's election with traverse of embodiment 5 in the reply filed on 04/14/26 is acknowledged. The traversal is on the ground(s) that there is not a serious burden upon the examiner. This is not found persuasive because at least the following reason(s) apply: the species or groupings of patentably indistinct species require a different field of search (e.g., searching different classes/subclasses or electronic resources, or employing different search strategies or search queries).
The requirement is still deemed proper and is therefore made FINAL.
Claim Objections
Claim 8 is objected to because of the following informalities: “is located between” is repeated in line 2 and one of these occurrences must be deleted. Appropriate correction is required.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim(s) 1-2, 6-8, and 23 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Kim et al., US 2023/0065378.
Kim et al. shows the invention as claimed including a repackaging structure 10, comprising:
A substrate 100, comprising a plate 100, a plurality of mounting pads 155 and a plurality of corresponding pads 120, wherein the plurality of corresponding pads and the plurality of mounting pads are disposed on opposite surfaces of the plate, and the plurality of corresponding pads correspond to the plurality of mounting pads;
At least one chip 210, mounted on the substrate and comprising a plurality of chip leads 211, wherein the plurality of chip leads are mounted on the plurality of mounting pads 155;
A dielectric body 410/420, covering the at least one chip;
An electrical element 220, disposed on the dielectric body; and
At least one conductive pillar 312, electrically connecting the electrical element and the substrate (see fig. 1B and its description).
Concerning dependent claim 2, note that in Kim et al. the plurality of corresponding pads 120 respectively corresponds to the plurality of mounting pads 155.
Regarding dependent claim 6, note that Kim et al. discloses the repackaging structure further comprising a buffer connection layer 510, wherein the at least one chip is mounted on the substrate through the buffer connection layer.
With respect to dependent claim 7, note that Kim et al. discloses wherein the buffer connection layer comprises a plurality of conductive solder blocks.
As to dependent claim 8, Kim et al. discloses a portion of the dielectric body 410 is located between the plurality of conductive solder blocks 510.
Concerning dependent claim 23, note that the substrate further comprises a plurality of conductive-via-connection structures, each of the plurality of corresponding pads corresponds to and is electrically connected to each of the plurality of mounting pads through each of the plurality of conductive-via-connection structures.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention.
Claim(s) 3-4, 22, and 25-27 is/are rejected under 35 U.S.C. 103 as being unpatentable over Kim et al., US 2023/0065378.
Kim et al. is applied as above but does not expressly disclose wherein a number of the plurality of chip leads is equal to a number of the plurality of mounting pads and the number of the plurality of mounting pads is equal to a number of the plurality of corresponding pads. However, it would have been obvious to one of ordinary skill in the art at the time the invention was filed to determine through routine experimentation the optimum number of chip leads, mounting pads and corresponding pads depending upon the desired number of connections and such limitation would not lend patentability to the instant invention absent a showing of unexpected results. Moreover, duplication of parts has been held to have been obvious.
As to dependent claim 4, Kim et al. is applied as above and additionally discloses where the number of the plurality of mounting pads is larger than the number of corresponding pads. However, Kim et al. does not expressly disclose wherein a number of the plurality of chip leads is equal to a number of the plurality of mounting pads. However, it would have been obvious to one of ordinary skill in the art at the time the invention was filed to determine through routine experimentation the optimum number of chip leads and mounting pads depending upon the desired number of connections and such limitation would not lend patentability to the instant invention absent a showing of unexpected results. Moreover, duplication of parts has been held to have been obvious.
Regarding dependent claim 22, Kim et al. does not disclose the percentage of the top view area of the dielectric body in comparison with the top view area of the at least one chip. However, it would have been obvious to one of ordinary skill in the art at the time the invention was made to determine through routine experimentation the optimum top view area of the dielectric body and at least one chip depending upon the desired design of the packaging device. Additionally, where the only difference between the prior art and the claims was a recitation of relative dimensions of the claimed device and a device having the claimed relative dimensions would not perform differently than the prior art device, the claimed device was not patentably distinct from the prior art device.
Concerning independent claim 25, Kim et al. is applied as above but does not expressly disclose where the chip leads include a plurality of signal leads and at least one other lead. However, note that Kim et al. discloses a plurality of chip leads 211, and the examiner takes official notice that it would have been obvious to one of ordinary skill in the art at the time the invention was filed to have the chip leads formed of signal leads or other leads depending upon the desires of the circuit or chip designer.
As to dependent claims 26-27, note that Kim et al. discloses a dielectric body, covering the at least one chip; an electrical element, disposed on the dielectric body; and at least one conductive pillar, electrically connecting the electrical element and the substrate.
Claim(s) 10-12 is/are rejected under 35 U.S.C. 103 as being unpatentable over Kim et al., US 2023/0065378 in view of Palmer, U.S. Patent 5,721,454.
Kim et al. is applied as above but does not expressly disclose wherein the substrate further comprises at least one ground pad connected to a ground layer, and a conductive layer electrically connected to the at least one ground pad through a conductive pillar.
Palmer discloses a ground pad 30 connected to a ground layer 34, and a conductive layer 38 electrically connected to a ground pad through a conductive pillar (see fig. 1 and its description). In view of this disclosure, it would have been obvious to one of ordinary skill in the art at the time the invention was filed to modify the primary reference of Kim et al. to form the ground layer/pad configuration of Palmer as this is shown as an effective method to interconnect conductive features.
Allowable Subject Matter
Claims 5 and 13-15 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Claim 24 is allowed.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. Hsiao et al., US 2007/0158828 discloses the formation of a package involving a conductive pillar 22, and Kang et al., US 2009/0166840 discloses the formation of conductive pillars 140 on stacked semiconductor chips.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to RICHARD A BOOTH whose telephone number is (571)272-1668. The examiner can normally be reached Monday to Friday, 8:30 to 5:00.
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/RICHARD A BOOTH/ Primary Examiner, Art Unit 2812
July 13, 2026
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