DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Amendment
The amendment filed on 6/2/2026 has been considered.
Response to Arguments
Applicant's arguments filed on 6/2/2026 have been considered but they are not persuasive.
Regarding the amended claim 15, the applicant argues the rejection under 35 USC 102(a)(1) is improper because Wada (US 2011/0227096) does not disclose the newly added claim limitation of “a first channel region in the first body region ;a second channel region in the second body region; and including a gate conductive region and a gate dielectric region, the gate dielectric region being positioned partially between the gate conductive region and the first source region, partially between the gate conductive region and the first channel region, partially between the gate conductive region and the second source region, partially between the gate conductive region and the second channel region, the gate dielectric region and the gate conductive region being positioned above the first and second source regions and above the first and second channel regions”. The examiner respectfully disagrees. Figure 21 and related text of Wada disclose a first channel region (region of left 13 under 17, figure) in the first body region (left 13, [75], figure); a second channel region (region of right 13 under 17, figure) in the second body region (right 13, [75], figure); including a gate conductive region (17, [80]) and a gate dielectric region (15, [80]), the gate dielectric region (15, [80]) being positioned partially between the gate conductive region (17, [80]) and the first source region (left 14, [75], figure), partially between the gate conductive region (17, [80]) and the first channel region (region of left 13 under 17, figure), partially between the gate conductive region (17, [80]) and the second source region (right 14, [75], figure), partially between the gate conductive region (17, [80]) and the second channel region (region of right 13 under 17, figure), the gate dielectric region (15, [80]) and the gate conductive region (17, [80]) being positioned above the first (left 14, [75], figure) and second (right 14, [75], figure) source regions and above the first (region of left 13 under 17, figure) and second (region of right 13 under 17, figure) channel regions. Therefore, the examiner maintains the rejection.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim(s) 15-16 and 18-20 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Wada (US 2011/0227096).
Regarding claim 15, Wada discloses, in at least figure 21 and related text, a device, comprising:
a substrate (11/12, [75]) including:
a drain region (11/12, [75]) having a first conductivity type;
first (left 13, [75], figure) and second (right 13, [75], figure) body regions having a second conductivity type and in the drain region (11/12, [75]), the first (left 13, [75], figure) and second (right 13, [75], figure) body regions separated from each other by a portion of the drain region (11/12, [75]);
a first channel region (region of left 13 under 17, figure) in the first body region (left 13, [75], figure);
a second channel region (region of right 13 under 17, figure) in the second body region (right 13, [75], figure); and
first (left 14, [75], figure) and second (right 14, [75], figure) source regions having the first conductivity type, the first (left 14, [75], figure) and second (right 14, [75], figure) source regions in the first (left 13, [75], figure) and second (right 13, [75], figure) body regions, respectively;
an insulated gate region (15/17/21, [80], [138]) directly overlying the portion of the drain region (11/12, [75]) and including a gate conductive region (17, [80]) and a gate dielectric region (15, [80]), the gate dielectric region (15, [80]) being positioned partially between the gate conductive region (17, [80]) and the first source region (left 14, [75], figure), partially between the gate conductive region (17, [80]) and the first channel region (region of left 13 under 17, figure), partially between the gate conductive region (17, [80]) and the second source region (right 14, [75], figure), partially between the gate conductive region (17, [80]) and the second channel region (region of right 13 under 17, figure), the gate dielectric region (15, [80]) and the gate conductive region (17, [80]) being positioned above the first (left 14, [75], figure) and second (right 14, [75], figure) source regions and above the first (region of left 13 under 17, figure) and second (region of right 13 under 17, figure) channel regions; and
a first barrier region (210, [87]) on the insulated gate region (15/17/21, [80], [138]).
Regarding claim 16, Wada discloses the device of claim 15 as described above.
Wada further discloses, in at least figure 21 and related text, a first insulating layer (15, [80]) on the substrate (11/12, [75]);
a conductive layer (17, [80]) on the first insulating layer (15, [80]); and
a second insulating layer (21, [138]) on the conductive layer (17, [80]).
Regarding claim 18, Wada discloses the device of claim 15 as described above.
Wada further discloses, in at least figure 21 and related text, the first barrier region (210, [87]) includes silicon nitride ([87]).
Regarding claim 19, Wada discloses the device of claim 15 as described above.
Wada further discloses, in at least figure 21 and related text, the first source region (left 14, [75], figure) includes a body contact region (18, [75]) having the second conductivity type.
Regarding claim 20, Wada discloses the device of claim 15 as described above.
Wada further discloses, in at least figure 21 and related text, a metallization layer (27, [84]) on the first barrier region (210, [87]).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 1, 3-5, 7 and 10-14 is/are rejected under 35 U.S.C. 103 as being unpatentable over Lee (US 2015/0091084) in view of Wada (US 2011/0227096).
Regarding claim 1, Lee discloses, in at least figure 2 and related text, a metal oxide semiconductor field effect transistor (MOSFET) device ([197], [198], figure) comprising:
a semiconductor body (3/6, [52]);
a plurality of source regions (45a/45b, [82]) of a first conductivity type in the semiconductor body (3/6, [52]);
a plurality of body regions (33a/33b, [79]) of a second conductivity type in the semiconductor body (6, [52]), the plurality of body regions (33a/33b, [79]) including a plurality of channel regions (region of 33a/33b contacting with 36, figure);
a drain region (3/6, [52]) of the first conductivity type in the semiconductor body (3/6, [52]); a plurality of insulated gate regions (region of 36/39’, [57], [92]), each of the plurality of insulated gate regions (region of 36/39’, [57], [92]) including:
a gate conductive region (39’, [92]); and
a gate dielectric region (36, [57]) partially interposed between the gate conductive region (39’, [92]) and a corresponding source region (45a/45b, [82]) and partially interposed between the gate conductive region (39’, [92]) and a corresponding channel region (region of 33a/33b contacting with 36, figure); and
a plurality of barrier structures (54a, [58]), each of the plurality of barrier structures (54a, [58]) extending on a corresponding insulated gate region (region of 36/39’, [57], [92]) and including a first barrier region of silicon nitride (52b, [58]).
Lee does not explicitly disclose the gate dielectric region and the gate conductive region being positioned above the corresponding source region and the corresponding channel region.
Wada teaches, in at least figure 21 and related text, the device comprising the gate dielectric region (15, [80]) and the gate conductive region (17, [80]) being positioned above the corresponding source region (14, [75]) and the corresponding channel region (region of 13 under 17, figure), for the purpose of providing semiconductor device having a construction capable of achieving suppressed deterioration of electric characteristics in an insulating member ([14]).
Lee and Wada are analogous art because they both are directed to semiconductor device and one of ordinary skill in the art would have had a reasonable expectation of success to modify Lee with the specified features of Wada because they are from the same field of endeavor.
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have modified the structure disclosed in Lee to have the gate dielectric region and the gate conductive region being positioned above the corresponding source region and the corresponding channel region, as taught by Wada, for the purpose of providing semiconductor device having a construction capable of achieving suppressed deterioration of electric characteristics in an insulating member ([14], Wada).
Regarding claim 3, in view of Wada discloses the MOSFET device according to claim 1 as described above.
Wada further teaches, in at least figure 21 and related text, the first barrier region (210, [80]) overlies, at a distance, the corresponding channel region (region of 13 under 17, figure), for the purpose of providing semiconductor device having a construction capable of achieving suppressed deterioration of electric characteristics in an insulating member ([14]).
Regarding claim 4, Lee in view of Wada discloses the MOSFET device according to claim 1 as described above.
Lee further discloses, in at least figure 2 and related text, each of the plurality of barrier structures (54a, [58]) includes an insulating region (52a, [58]) on and in direct contact with a corresponding gate conductive region (39’, [92]), and
each first barrier region (52b, [58]) is on a corresponding insulating region (52a, [58]).
Regarding claim 5, Lee in view of Wada discloses the MOSFET device according to claim 1 as described above.
Lee further discloses, in at least figure 2 and related text, each of the plurality of barrier structures (54a, [58]) includes an insulating region (52a, [58]) on and in direct contact with a corresponding first barrier region (52b, [58]).
Regarding claim 7, Lee in view of Wada discloses the MOSFET device according to claim 1 as described above.
Lee further discloses, in at least figure 2 and related text, the gate conductive regions (39’, [92]) include polysilicon ([92]).
Regarding claim 10, Lee in view of Wada discloses the MOSFET device according to claim 1 as described above.
Wada further teaches, in at least figure 21 and related text, the device comprising the semiconductor body (11/12, [75]) is delimited by a first surface (upper surface of 12, figure); the plurality of body regions (13, [75]) extend inside the drain region (11/12, [75]), starting from the first surface (upper surface of 12, figure), and are laterally staggered, in such a way that pairs of adjacent body regions (13, [75]) are separated by a corresponding surface portion of the drain region (11/12, [75]), which faces the first surface (upper surface of 12, figure); each of the plurality of source regions (14, [75]) extends inside a corresponding body region (13, [75]), the plurality of channel regions (region of 13 contacting 15, figure) being formed by portions of the plurality of body regions (13, [75]) that are arranged laterally with respect to the plurality of source regions (14, [75]) and face the first surface (upper surface of 12, figure); the gate dielectric region (15, [80]) extends on the first surface (upper surface of 12, figure) and overlies a corresponding surface portion of the drain region (11/12, [75]), corresponding channel regions (region of 13 contacting 15, figure) and portions of corresponding source regions (14, [75]); the gate conductive region (17, [80]) extends on the gate dielectric region (15, [80]), for the purpose of providing semiconductor device having a construction capable of achieving suppressed deterioration of electric characteristics in an insulating member ([14]).
Regarding claim 11, Lee in view of Wada discloses the MOSFET device according to claim 1 as described above.
Lee further discloses, in at least figure 2 and related text, the semiconductor body (3/6, [52]) is delimited by a first surface (upper surface of 6, figure);
wherein the plurality of source regions (45a/45b, [82]) face the first surface (upper surface of 6, figure) and overlie corresponding body regions (33a/33b, [79]);
wherein each of the plurality of insulated gate regions (region of 36/39’, [57], [92]) extends inside a corresponding trench (trench for 36/39’, figure), which extends inside the semiconductor body (3/6, [52]), starting from the first surface (upper surface of 6, figure), and is interposed between a corresponding pair of source regions (45a/45b, [82]) and a corresponding pair of body regions (33a/33b, [79]);
wherein the gate conductive region (39’, [92]) and the gate dielectric region (36, [57]) extend inside the corresponding trench (trench for 36/39’, figure), the gate dielectric region (36, [57]) surrounding the gate conductive region (39’, [92]) and contacting the corresponding pair of source regions (45a/45b, [82]) and the corresponding pair of body regions (33a/33b, [79]); and
wherein the plurality of channel regions (region of 33a/33b contacting with 36, figure) are formed by portions of the body regions (33a/33b, [79]) that contact gate dielectric regions (36, [57]).
Regarding claim 12, Lee discloses, in at least figures 2, 7A-7V, and related text, a process for manufacturing a metal oxide semiconductor field effect transistor (MOSFET) device comprising:
forming a plurality of source regions (45a/45b, [82]) of a first conductivity type in a semiconductor body (3/6, [52]);
forming a plurality of body regions (33a/33b, [79]) of a second conductivity type in the semiconductor body (3/6, [52]), the plurality of body regions (33a/33b, [79]) including a plurality of channel regions (region of 33a/33b contacting with 36, figure 2);
forming a drain region (3/6, [52]) of the first conductivity type in the semiconductor body (3/6, [52]);
forming a plurality of insulated gate regions (region of 36/39’, [57], [92]), each of the plurality of insulated gate regions (region of 36/39’, [57], [92]) including:
a gate conductive region (39’, [92]); and
a gate dielectric region (36, [57]) partially interposed between the gate conductive region (39’, [92]) and a corresponding source region (45a/45b, [82]) and partially interposed between the gate conductive region (39’, [92]) and a corresponding channel region (region of 33a/33b contacting with 36, figure 2); and
forming a plurality of barrier structures (54a, [58]), each of the plurality of barrier structures (54a, [58]) extending on a corresponding insulated gate region (region of 36/39’, [57], [92]) and including a barrier region of silicon nitride (52b, [58]).
Lee does not explicitly disclose the gate dielectric region and the gate conductive region are positioned above the corresponding source region and the corresponding channel region.
Wada teaches, in at least figure 21 and related text, the method comprising the gate dielectric region (15, [80]) and the gate conductive region (17, [80]) are positioned above the corresponding source region (14, [75]) and the corresponding channel region (region of 13 under 17, figure), for the purpose of providing semiconductor device having a construction capable of achieving suppressed deterioration of electric characteristics in an insulating member ([14]).
Lee and Wada are analogous art because they both are directed to method for forming a semiconductor device and one of ordinary skill in the art would have had a reasonable expectation of success to modify Lee with the specified features of Wada because they are from the same field of endeavor.
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have modified the method disclosed in Lee to have the gate dielectric region and the gate conductive region being positioned above the corresponding source region and the corresponding channel region, as taught by Wada, for the purpose of providing semiconductor device having a construction capable of achieving suppressed deterioration of electric characteristics in an insulating member ([14], Wada).
Regarding claim 13, Lee in view of Wada discloses the process according to claim 12 as described above.
Lee further discloses, in at least figures 2, 7A-7V, and related text, forming the plurality of barrier structures (54a, [58]) includes forming a silicon nitride layer (layer of 51b, [179]) on the plurality of insulated gate regions (region of 36/39’, [57], [92]), and subsequently selectively removing portions of the silicon nitride layer (layer of 51b, [179]) (figures 7Q-7S).
Regarding claim 14, Lee in view of Wada discloses the process according to claim 13 as described above.
Lee further discloses, in at least figures 2, 7A-7V, and related text, forming an oxide layer (51a, [179]) on the gate conductive regions (39’, [92]), in direct contact,
wherein forming the silicon nitride layer (52b, [58]) includes forming the silicon nitride layer (51b, [179]) on the oxide layer (51a, [179]).
Claim(s) 2 is/are rejected under 35 U.S.C. 103 as being unpatentable over Lee (US 2015/0091084) in view of Wada (US 2011/0227096).
Regarding claim 2, Lee in view of Wada discloses the MOSFET device according to claim 1 as described above.
Lee in view of Wada does not explicitly disclose the first barrier region has a thickness greater than or equal to 30 nanometers.
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to provide the thickness of first barrier region as claimed in claim 2 in order to optimize the performance of the device in .. It is noted that the selection dimension of the thickness of the first barrier region as being no more than use of known technique to improve similar devices in the same way. See MPEP 2143 I. C. It is noted that if a technique has been used to improve one device, and a person of ordinary skill in the art would recognize that it would improve similar devices in the same way, using the technique is obvious unless its actual application is beyond that person's skill. KSR International Co. v. Teleflex Inc., 550 US 398, 82 USPQ2d 1385, 1389 (2007). In Gardnerv.TEC Syst., Inc., 725 F.2d 1338, 220 USPQ 777 (Fed. Cir. 1984), cert. denied, 469 U.S. 830, 225 USPQ 232 (1984), the Federal Circuit held that, where the only difference between the prior art and the claims was a recitation of relative dimensions of the claimed device and a device having the claimed relative dimensions would not perform differently than the prior art device, the claimed device was not patentably distinct from the prior art device.
Furthermore, it has been held that where the general conditions of a claim are disclosed in the prior art, discovering the optimum or workable ranges involves only routine skill in the art. In re Aller, 105 USPQ 233.
The specification contains no disclosure of either the critical nature of the claimed arrangement (i.e.- the first barrier region has a thickness greater than or equal to 30 nanometers) or any unexpected results arising therefrom.
Where patentability is said to be based upon particular chosen limitations or upon another variable recited in a claim, the applicant must show that the chosen limitations are critical. In re Woodruff, 919 F.2d 1575, 1578 (FED. Cir. 1990).
Claim(s) 8-9 is/are rejected under 35 U.S.C. 103 as being unpatentable over Lee (US 2015/0091084) in view of Wada (US 2011/0227096), and further in view of Nagata (US 2022/0181447).
Regarding claim 8, Lee discloses the MOSFET device according to claim 1 as described above.
Lee does not explicitly disclose a plurality of body contact regions of the second conductivity type in the plurality of source regions, each of the plurality of body contact regions extending inside a corresponding source region, starting from a front surface of the semiconductor body, up to contacting an underlying corresponding body region.
Nagata teaches, in at least figure 10 and related text, the device comprising a plurality of body contact regions (98, [253]) of the second conductivity type in the plurality of source regions (97, [252]), each of the plurality of body contact regions (98, [253]) extending inside a corresponding source region (97, [252]), starting from a front surface of the semiconductor body (62, [171]), up to contacting an underlying corresponding body region (74, [191]) (figure), for the purpose of providing SiC semiconductor device with which an external force can be relaxed ([6]) thereby preventing cracks.
Lee and Nagata are analogous art because they both are directed to semiconductor device and one of ordinary skill in the art would have had a reasonable expectation of success to modify Lee with the specified features of Nagata because they are from the same field of endeavor.
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have modified the structure disclosed in Lee to have the plurality of body contact regions of the second conductivity type in the plurality of source regions, each of the plurality of body contact regions extending inside a corresponding source region, starting from a front surface of the semiconductor body, up to contacting an underlying corresponding body region, as taught by Nagata, for the purpose of providing SiC semiconductor device with which an external force can be relaxed ([6], Nagata) thereby preventing cracks.
Regarding claim 9, Lee in view of Nagata discloses the MOSFET device according to claim 8 as described above.
Lee further discloses, in at least figure 2 and related text, a source metallization (72, [86]), which partially overlies the plurality of barrier structures (54a, [58]) and in part extends through the plurality of barrier structures (54a, [58]), in contact with the plurality of source regions (45a/45b, [82]) and the plurality of body contact regions (66a/66b, [71]).
Allowable Subject Matter
Claim 6 is objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims because the prior art of record neither anticipates nor render obvious the limitations of the base claims 1, 5, and 6 that recite "each of the plurality of barrier structures includes a second barrier region of silicon nitride on a corresponding insulating region" in combination with other elements of the base claims 1, 5, and 6.
Claim 17 is objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims because the prior art of record neither anticipates nor render obvious the limitations of the base claims 15, 16 and 17 that recite "a second barrier region on the first barrier region" in combination with other elements of the base claims 15, 16 and 17.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to TONG-HO KIM whose telephone number is (571)270-0276. The examiner can normally be reached Monday thru Friday; 8:30 AM to 5PM.
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/TONG-HO KIM/ Primary Examiner, Art Unit 2811
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