DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Priority
Receipt is acknowledged of certified copies of papers required by 37 CFR 1.55.
Election/Restrictions
Claims 15-20 are withdrawn from further consideration pursuant to 37 CFR 1.142(b) as being drawn to a nonelected invention, there being no allowable generic or linking claim. Election was made without traverse in the reply filed on 13 April 2026. Applicants are reminded to indicate the withdrawn status of claims 15-20 in their next submission of a claim listing.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim(s) 1-3 and 9-14 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Wang et al. (CN113270421B).
Regarding claim 1, Wang teaches in Fig. 5A a semiconductor device, comprising:
a stacked layer (200) {[0045]};
a top select gate layer (630) located on the stacked layer (200) {Fig. 4A; [0084]};
a gate-line structure (400) extending through the top select gate layer (630) and the stacked layer (200), wherein a portion of the gate-line structure (400) that extends through the top select gate layer (630) comprises a first isolation structure (430), and the first isolation structure (430) comprises a contact layer (portion of 430 within 600) in contact with the top select gate layer (630) {[0107]};
a channel structure (300) extending through the stacked layer (200) {[0105]};
a first dielectric layer (650, 610/611, and/or 620/621 above 630) located on the top select gate layer (630), wherein the first dielectric layer (650, 610/611, and/or 620/621 above 630) and the contact layer (portion of 430 within 600) comprise different insulating materials {[0053]; [0093], 430 is silicon oxide; [0055, 0056], 610 and 650 are silicon oxide, silicon oxynitride, silicon nitride, TEOS, or doped silicon oxide; and [0056], 620 is silicon oxide, silicon oxynitride, or silicon nitride}; and
a channel local contact (606 and/or 640) extending through the first dielectric layer (650, 610, and/or 620 above 630) and corresponding to the channel structure (300) {[0071, 0101]}.
Regarding claim 2, Wang teaches the semiconductor device of claim 1, and Wang further teaches further comprising:
a connecting structure (602) extending through the top select gate layer (630), wherein one end of the connecting structure (602) is in contact with the channel structure (300) and the other end of the connecting structure (602) is in contact with the channel local contact (606 and/or 640) {[0071]}.
Regarding claim 3, Wang teaches the semiconductor device of claim 2, and Wang further teaches further comprising:
a second dielectric layer (610/611, and/or 620/621 above 630) located between the top select gate layer (630) and the first dielectric layer (650, 610/611, and/or 620/621 above 630), wherein the connecting structure (602) extends through the second dielectric layer (610/611, and/or 620/621 above 630) to be in contact with the channel local contact (606 and/or 640) {[0053, 0055, 0056]}.
Regarding claim 9, Wang teaches the semiconductor device of claim 1, and Wang further teaches further comprising:
a semiconductor layer (100) provided on a side of the stacked layer (200) away from the top select gate layer (630) {[0047]}.
Regarding claim 10, Wang teaches the semiconductor device of claim 3, and Wang further teaches further comprising:
a cap layer (650) provided on the first dielectric layer (620/621 above 630), wherein the channel local contact (606 and 640) extends through the cap layer (650) and the first dielectric layer (620/621 above 630) and is in contact with the channel structure (300) {Figs. 2, 5B; [0096]}.
Regarding claim 11, Wang teaches the semiconductor device of claim 10, and Wang further teaches wherein:
the first dielectric layer (620/621 above 630) and the cap layer (650) comprise different insulating materials {[0053]; [0055, 0056], 650 is silicon oxide, silicon oxynitride, silicon nitride, TEOS, or doped silicon oxide; and [0056], 620/621 is silicon oxide, silicon oxynitride, or silicon nitride}; and
the first dielectric layer (620/621 above 630) and the second dielectric layer (610/611 above 630) comprise different insulating materials {[0053]; [0055, 0056], 610/611 is silicon oxide, silicon oxynitride, silicon nitride, TEOS, or doped silicon oxide; and [0056], 620/621 is silicon oxide, silicon oxynitride, or silicon nitride}.
Regarding claim 12, Wang teaches the semiconductor device of claim 1, and Wang further teaches further comprising:
a top select gate cut (604) located between the first dielectric layer (650, 610/611, and/or 620/621 above 630) and the stacked layer (200) and extending through the top select gate layer (630), wherein the top select gate cut (604) and the first dielectric layer (650, 610/611, and/or 620/621 above 630) comprise the same insulating material or different insulating materials {[0056, 0098]}.
Regarding claim 13, Wang teaches the semiconductor device of claim 12, and Wang further teaches wherein the different insulating materials comprise at least two of silicon nitride, insulation oxide, or silicon oxynitride {[0056, 0098]}.
Regarding claim 14, Wang teaches in Fig. 5A a semiconductor device, comprising:
a stacked layer (200) {[0045]};
a top select gate layer (630) located on the stacked layer (200) {Fig. 4A; [0084]};
a gate-line structure (400) extending through the top select gate layer (630) and the stacked layer (200) {[0107]};
a channel structure (300) extending through the stacked layer (200) {[0105]};
a first dielectric layer (650, 610/611, and/or 620/621 above 630) located on the top select gate layer (630) and covering the gate-line structure (400) {[0053]}; and
a channel local contact (606 and/or 640) extending through the first dielectric layer (650, 610/611, and/or 620/621 above 630) and corresponding to the channel structure (300) {[0071, 0101]}.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 4 and 8 is/are rejected under 35 U.S.C. 103 as being unpatentable over Wang as applied to claim 3 and claim 1 respectively above, and further in view of Zhu et al. (US20210020653A1).
Regarding claim 4, Wang teaches the semiconductor device of claim 3, and Wang further teaches wherein:
a portion (portion of 400 within 200) of the gate-line structure (400) that extends through the stacked layer (200) comprises a second isolation structure (portion of 400 within 200).
Wang does not teach a width of the first isolation structure is greater than a width of the second isolation structure in a direction parallel to the first dielectric layer.
In an analogous art, Zhu teaches in Fig. 5G and paragraph [0086] a width of a first isolation structure (portion of 540 in 526 and/or 528) is greater than a width of a second isolation structure (portion of 540 in 536) in a direction parallel to a first dielectric layer (528 and/or 550). It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify Wang’s semiconductor device based on the teachings of Zhu – such that a width of the first isolation structure is greater than a width of the second isolation structure in a direction parallel to the first dielectric layer – because an etched trench structure naturally narrows with increasing depth of the trench due to limitations of the etching process. Moreover, all the claimed elements (e.g., width of the first isolation structure, width of the second isolation structure) were known in the prior art and one skilled in the art could have combined the elements as claimed by known methods (e.g., as taught by Zhu) with no change in their respective functions, and the combination yielding nothing more than predictable results to one of ordinary skill in the art. MPEP §2143(I)(A). Furthermore, [t]he selection of a known … [structure] based on its suitability for its intended use [is] … prima facie obviousness. MPEP §2144.07.
Regarding claim 8, Wang teaches the semiconductor device of claim 1, but Wang does not teach further comprising:
a conductive core extending through the first dielectric layer and communicating with the gate-line structure.
Zhu teaches in Fig. 5G and paragraph [0087] a conductive core (558) extending through a first dielectric layer (550) and communicating with the gate-line structure (546). It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify Wang’s semiconductor device based on the teachings of Zhu – to include a conductive core extending through the first dielectric layer and communicating with the gate-line structure – to provide electrical connectivity between the gate-line structure and an external environment. Moreover, all the claimed elements (e.g., conductive core, first dielectric layer, gate-line structure) were known in the prior art and one skilled in the art could have combined the elements as claimed by known methods (e.g., as taught by Zhu) with no change in their respective functions, and the combination yielding nothing more than predictable results to one of ordinary skill in the art. MPEP §2143(I)(A). Furthermore, [t]he selection of a known … [structure] based on its suitability for its intended use [is] … prima facie obviousness. MPEP §2144.07.
Claim(s) 5 is/are rejected under 35 U.S.C. 103 as being unpatentable over Wang as applied to claim 3 above, and further in view of Iwata et al. (US20240237345A1).
Regarding claim 5, Wang teaches the semiconductor device of claim 3, and Wang further teaches wherein the semiconductor device further comprises:
a first contact structure (a different 606 and/or 640 than that of the channel local contact) provided in the core array (core array illustrated by Fig. 5A), extending through the first dielectric layer (650, 610, and/or 620 above 630) and the second dielectric layer (610 and/or 620 above 630) and extending to the top select gate layer (630).
Wang does not teach:
a core array and a staircase, the top select gate layer is provided in the core array; and
a second contact structure provided in the staircase, extending through the first dielectric layer and extending to a step of the staircase.
In an analogous art, Iwata teaches in Fug. 23 a core array (100) and a staircase (200), a top select gate layer (146) is provided in the core array {[0102]; [0232], first electrically conductive layers 146 (which function as first word lines and select gate electrodes)}; and a second contact structure (86) provided in the staircase (200), extending through a first dielectric layer (280 and/or 282) and extending to a step of the staircase (200) {[0201]}. It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify Wang’s semiconductor device based on the teachings of Iwata – such that a core array and a staircase, the top select gate layer is provided in the core array; and a second contact structure provided in the staircase, extending through the first dielectric layer and extending to a step of the staircase – to provide: (1) a select gate for differentiating different memory regions of a memory device and (2) a contact structure for differentiating a particular memory location (e.g., word line) from others. Moreover, all the claimed elements (e.g., core array, staircase, top select gate layer, second contact structure, first dielectric layer, step of the staircase) were known in the prior art and one skilled in the art could have combined the elements as claimed by known methods (e.g., as taught by Iwata) with no change in their respective functions, and the combination yielding nothing more than predictable results to one of ordinary skill in the art. MPEP §2143(I)(A). Furthermore, [t]he selection of a known … [structure] based on its suitability for its intended use [is] … prima facie obviousness. MPEP §2144.07.
Claim(s) 6 is/are rejected under 35 U.S.C. 103 as being unpatentable over Wang in view of Iwata as applied to claim 5 above, and further in view of Shoji et al. (US20160204122A1) and Nakamura et al. (US20240038667A1).
Regarding claim 6, Wang as modified by Iwata teaches the semiconductor device of claim 5, but Wang does not teach wherein:
the first contact structure comprises a first substructure extending through the first dielectric layer and a second substructure extending through the second dielectric layer, and in a direction parallel to the first dielectric layer, at a position where the first substructure and the second substructure are connected with each other, a width of the first substructure is greater than a width of the second substructure; and
the second contact structure comprises a third substructure extending through the first dielectric layer and a fourth substructure extending to the step of the staircase, and in the direction parallel to the first dielectric layer, at a position where the third substructure and the fourth substructure are connected with each other, a width of the third substructure is greater than a width of the fourth substructure.
In an analogous art, Shoji teaches in Fig. 10 and paragraph [0109] a first contact structure (88) comprises a first substructure (portion of 88 within 73) extending through a first dielectric layer (73) and a second substructure (portion of 88 within 72) extending through a second dielectric layer (72), and in a direction (horizontal) parallel to the first dielectric layer (73), at a position where the first substructure (portion of 88 within 73) and the second substructure (portion of 88 within 72) are connected with each other, a width of the first substructure (portion of 88 within 73) is greater than a width of the second substructure (portion of 88 within 72). It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify Wang’s semiconductor device as modified by Iwata based on the teachings of Shoji – such that the first contact structure comprises a first substructure extending through the first dielectric layer and a second substructure extending through the second dielectric layer, and in a direction parallel to the first dielectric layer, at a position where the first substructure and the second substructure are connected with each other, a width of the first substructure is greater than a width of the second substructure – because an etched trench structure naturally narrows with increasing depth of the trench due to limitations of the etching process. Moreover, all the claimed elements (e.g., first contact structure, first substructure, first dielectric layer, second substructure, second dielectric layer, width) were known in the prior art and one skilled in the art could have combined the elements as claimed by known methods (e.g., as taught by Shoji) with no change in their respective functions, and the combination yielding nothing more than predictable results to one of ordinary skill in the art. MPEP §2143(I)(A). Furthermore, [t]he selection of a known … [structure] based on its suitability for its intended use [is] … prima facie obviousness. MPEP §2144.07.
In an analogous art, Nakamura teaches in Fig. 15 and paragraph [0118] a second contact structure (86) comprises a third substructure (portion of 86 within 73) extending through a first dielectric layer (73) and a fourth substructure (portion of 86 within 65) extending to a step (46) of a staircase (300), and in the direction (horizontal) parallel to the first dielectric layer (73), at a position where the third substructure (portion of 86 within 73) and the fourth substructure (portion of 86 within 65) are connected with each other, a width of the third substructure (portion of 86 within 73) is greater than a width of the fourth substructure (portion of 86 within 65). It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify Wang’s semiconductor device as modified by Iwata and Shoji based on the teachings of Nakamura – such that the second contact structure comprises a third substructure extending through the first dielectric layer and a fourth substructure extending to the step of the staircase, and in the direction parallel to the first dielectric layer, at a position where the third substructure and the fourth substructure are connected with each other, a width of the third substructure is greater than a width of the fourth substructure – because an etched trench structure naturally narrows with increasing depth of the trench due to limitations of the etching process. Moreover, all the claimed elements (e.g., second contact structure, third substructure, first dielectric layer, fourth substructure, staircase, step, width) were known in the prior art and one skilled in the art could have combined the elements as claimed by known methods (e.g., as taught by Nakamura) with no change in their respective functions, and the combination yielding nothing more than predictable results to one of ordinary skill in the art. MPEP §2143(I)(A). Furthermore, [t]he selection of a known … [structure] based on its suitability for its intended use [is] … prima facie obviousness. MPEP §2144.07.
Claim(s) 7 is/are rejected under 35 U.S.C. 103 as being unpatentable over Wang in view of Iwata as applied to claim 5 above, and further in view of Shoji.
Regarding claim 7, Wang as modified by Iwata teaches the semiconductor device of claim 5, but Wang does not teach wherein:
in a direction parallel to the first dielectric layer, a portion of the channel local contact extending through the first dielectric layer has a first width, a portion of the first contact structure extending through the first dielectric layer has a second width, and a portion of the second contact structure extending through the first dielectric layer has a third width; and
the second width is greater than the first width, and the first width is greater than the third width.
Shoji teaches in Fig. 10 and paragraph [0111] in a direction (horizontal) parallel to a first dielectric layer (90), a portion of a channel local contact (92 disposed on 88) extending through the first dielectric layer (88) has a first width, a portion of a first contact structure (92 disposed on 76) extending through the first dielectric layer (88) has a second width, and a portion of the second contact structure (92 disposed on 8) extending through the first dielectric layer (88) has a third width; and the second width is greater than the first width, and the first width is greater than the third width. It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify Wang’s semiconductor device as modified by Iwata based on the teachings of Shoji – such that in a direction parallel to the first dielectric layer, a portion of the channel local contact extending through the first dielectric layer has a first width, a portion of the first contact structure extending through the first dielectric layer has a second width, and a portion of the second contact structure extending through the first dielectric layer has a third width; and the second width is greater than the first width, and the first width is greater than the third width – because the surface area of a contact structure is proportionate to the amount of current to be conducted therethrough. Moreover, all the claimed elements (e.g., first dielectric layer, channel local contact, first contact structure, second contact structure, width) were known in the prior art and one skilled in the art could have combined the elements as claimed by known methods (e.g., as taught by Shoji) with no change in their respective functions, and the combination yielding nothing more than predictable results to one of ordinary skill in the art. MPEP §2143(I)(A). Furthermore, [t]he selection of a known … [structure] based on its suitability for its intended use [is] … prima facie obviousness. MPEP §2144.07.
Citation of Pertinent Prior Art
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
Yang (US20240349506A1) teaches a memory device includes a substrate, a plurality of conductive layers, a plurality of dielectric layers, a memory structure, a select gate structure and a bit line contact. The conductive layers and the dielectric layers are interlaced and stacked on the substrate. The memory structure penetrates through the conductive layers and the dielectric layers, and the memory structure includes a channel structure and a conductive plug disposed on the channel structure. The select gate structure is disposed on a sidewall of the memory structure. The select gate structure includes a select gate dielectric layer and a select gate electrode surrounded by the select gate dielectric layer. A top surface of the select gate electrode is between a top surface of the conductive plug and a top surface of a topmost layer of the conductive layers. The bit line contact is electrically connected to the memory structure.
Conclusion
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/D.W.W./Examiner, Art Unit 2891
/MATTHEW C LANDAU/Supervisory Patent Examiner, Art Unit 2891
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