DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Election/Restrictions
Applicant’s election without traverse of Species A, claims 1-10, and 13-15 in the reply filed on 05/28/2026 is acknowledged.
Foreign Priority
Acknowledgment is made of applicant’s claim for foreign priority under 35 U.S.C. 119 (a)-(d). The certified copy has been filed in parent Application No. KR10-2022-0187263, filed on 12/28/2022.
Information Disclosure Statement
The information disclosure statement (IDS) submitted on 07/08/2024 and 12/26/2023 is in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statement is being considered by the examiner.
Drawings
The drawings are objected to under 37 CFR 1.83(a). The drawings must show every feature of the invention specified in the claims. Therefore, the “some of the plurality of first assembling lines each comprise a jumping pattern disposed in an area in which some of the plurality of first assembling lines intersect another first assembling line, and wherein some of the plurality of second assembling lines each comprise a jumping pattern disposed in an area in which some of the plurality of second assembling lines intersect another second assembling line” must be shown or the feature canceled from the claim. No new matter should be entered.
Corrected drawing sheets in compliance with 37 CFR 1.121(d) are required in reply to the Office action to avoid abandonment of the application. Any amended replacement drawing sheet should include all of the figures appearing on the immediate prior version of the sheet, even if only one figure is being amended. The figure or figure number of an amended drawing should not be labeled as “amended.” If a drawing figure is to be canceled, the appropriate figure must be removed from the replacement sheet, and where necessary, the remaining figures must be renumbered and appropriate changes made to the brief description of the several views of the drawings for consistency. Additional replacement sheets may be necessary to show the renumbering of the remaining figures. Each drawing sheet submitted after the filing date of an application must be labeled in the top margin as either “Replacement Sheet” or “New Sheet” pursuant to 37 CFR 1.121(d). If the changes are not accepted by the examiner, the applicant will be notified and informed of any required corrective action in the next Office action. The objection to the drawings will not be held in abeyance.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claim 6 is rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention. Specifically, “some of the plurality of first assembling lines each comprise a jumping pattern disposed in an area in which some of the plurality of first assembling lines intersect another first assembling line, and wherein some of the plurality of second assembling lines each comprise a jumping pattern disposed in an area in which some of the plurality of second assembling lines intersect another second assembling line,” is not described in the specification or shown in the drawings.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claims 1, 3-4, 10, and 13 are rejected under 35 U.S.C. 102 as being anticipated by Nam et al. ( US 2023/0369345 A1; hereinafter Nam )
Regarding claim 1, Nam teaches a display device ( Fig. 6 display device 10 ), comprising: a substrate ( Fig. 6 substrate SUB ) comprising a display area ( Fig. 6 display area DPA ) in which a plurality of subpixels is disposed ( [0066] The display area DPA may include pixels PX ), and a non-display area ( Fig. 6 non-display area NDA ) disposed to surround the display area ( as shown in Fig. 6 ) and comprising a plurality of pad areas ( [0074] The first scan lines SL1 and the second scan lines SL2 may extend from a pad area PDA in the non-display area NDA to the display area DPA ); a plurality of pads disposed in the plurality of pad areas ( [0079 ] The wire pads WPD are illustrated as being disposed in the pad area PDA on the lower side of the display area DPA, but embodiments are not limited thereto ); a plurality of low-potential power link lines ( Fig. 5 VL2 described in para [0084] ) electrically connected to the pads ( [0079] the second voltage lines VL2 may be connected (e.g., electrically connected) to second voltage line wire pads WPD_VL2. ) disposed in leftmost and rightmost areas among the plurality of pad areas ( [0079] In another example, some of the wire pads WPD may be disposed on the upper side of the display area DPA or on the left or right side of the display area DPA ); a plurality of first assembling lines ( Fig. 7 first auxiliary electrodes FE1 ) and a plurality of second assembling lines ( Fig. 7 second auxiliary electrodes FE2 ) respectively disposed on the plurality of subpixels ( Fig. 7 subpixels SPX1, SPX2, and SPX3 ) and electrically connected to the plurality of low-potential power link lines ( [0195] the first auxiliary electrodes FE1 may be connected (e.g., electrically connected) to electrode layers 117 or second semiconductor layers 113 of the light-emitting elements ED, and the second auxiliary electrode FE2 may be connected (e.g., electrically connected) to first semiconductor layers 111 of the light-emitting elements ED; Fig. 9 ED connected to FE1 and FE2 which are connected to VL2 ); and a plurality of light-emitting elements ( Fig. 7: SPX1, SPX2, and SPX3 ) disposed on the plurality of first assembling lines ( Fig. 7: FE1 ) and the plurality of second assembling lines ( Fig. 7: FE2 ), wherein each of the plurality of low-potential power link lines comprises: a first part ( Fig. 9 shows how ED is connected to FE1 and FE2; Fig. 5 shows how EL is connected to VL2 ) connected to the plurality of first assembling lines ( Fig. 7: FE1 ) or the plurality of second assembling lines ( Fig. 7: FE2 ); and a second part ( [0078] the second voltage lines VL2, and the voltage lines VL may form a mesh structure over the entire display area DPA, but embodiments are not limited thereto ) configured to transmit a low-potential power voltage to the first part ( [0079] the second voltage lines VL2 may be connected (e.g., electrically connected) to one or more wire pads WPD ).
Regarding claim 3, Nam teaches the display device of claim 1 ( as discussed above), wherein an extension direction of the first part ( Fig. 5: VL2 ) intersects an extension direction of the plurality of first assembling lines ( Fig. 7: FE1 ) and an extension direction of the plurality of second assembling lines ( Fig. 7: FE2 ), and wherein at least a part of the second part ( [0078] the second voltage lines VL2, and the voltage lines VL may form a mesh structure over the entire display area DPA, but embodiments are not limited thereto) is parallel to the extension direction of the plurality of first assembling lines ( Fig. 7: FE1 ) and the extension direction of the plurality of second assembling lines ( Fig. 7: FE2 ).
Regarding claim 4, Nam teaches the display device of claim 1 ( as discussed above), further comprising: a plurality of transistors ( [0080] For example, the pixel driving circuit may have a “3T-1C” structure including three transistors and one capacitor ) disposed on the plurality of subpixels ( Fig. 7: SPX1, SPX2, and SPX3 ) and each comprising a gate electrode ( [0085] The gate electrode of the first transistor T1 may be connected (e.g., electrically connected) to the source electrode of the second transistor T2 ), a source electrode ( [0085] the source electrode of the first transistor T1 may be connected (e.g., electrically connected) to the first electrode of the LED EL ), a drain electrode ( [0085] the drain electrode of the first transistor T1 may be connected (e.g., electrically connected) to the first voltage line VL1 ), and an active layer ( [0111] the light-emitting elements ED may include active layers having the same material and may thus emit light of the same wavelength band or the same color ); and a light-blocking layer ( Fig. 6 first light-blocking members BK1 ) disposed between the plurality of transistors ( Fig. 5: T1, T2, and T3 ) and the substrate ( Fig. 6 SUB ), wherein the plurality of low-potential power link lines ( Fig. 3: VL2 ) is made of the same material ( [0078] The first voltage lines VL1 and the second voltage lines VL2 may be formed of the first conductive layer ) as at least one of the light-blocking layer, the source electrode, the drain electrode, the plurality of first assembling lines, and the plurality of second assembling lines ( [0172] The first auxiliary electrodes FE1 and the second auxiliary electrode FE2 may include a transparent conductive material. The transparent conductive material may include amorphous indium tin oxide (ITO), crystalline ITO, amorphous indium zinc oxide (IZO), and crystalline IZO ).
Regarding claim 10, Nam teaches the display device of claim 1 ( as discussed above), wherein the plurality of low-potential power link lines ( Fig. 3 VL2 ) each further comprises a third part ( as shown in Fig. 3 portion going in direction DR1 directly to the pad WPD_VL2 ) connected directly to the pad ( Fig. 3 WPD_VL2 ), and wherein the same voltages are applied to the second parts of the plurality of low-potential power link lines through the third parts ( all parts of VL2 are connected so are at the same Voltage as shown in Fig. 3 ).
Regarding claim 13, Nam teaches the display device of claim 1 ( as discussed above ), further comprising: a planarization layer ( Fig. 6 first planarization layer OC1 ) configured to cover the plurality of low-potential power link lines ( as shown in Fig. 5 VL2 is connected to EL which is part of ED ); and a plurality of pixel electrodes ( [0111] The light-emitting elements ED may be disposed on the first planarization layer OC1, between the first electrodes AE and the second electrodes CE ) disposed on the planarization layer ( Fig. 6: OC1 ) and connected to the plurality of light-emitting elements ( Fig. 6: light-emitting elements ED ).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 2 and 15 are rejected under U.S.C. 103 as being unpatentable over Nam et al.; US 2023/0369345 A1; 12/2022 in view of Kim et al.; EP 4064335 A1; 11/2019
Claim 2: Nam discloses the display device of claim 1 ( as discussed above).
Nam does not appear to disclose the plurality of pad areas is positioned at an upper side of the display area, wherein the first part is disposed in the non-display area between the plurality of pad areas and the display area or in the non-display area opposite to the plurality of pad areas, and wherein the second part is disposed in the non-display area at left and right sides of the display area.
However, Kim teaches the plurality of pad areas is positioned at an upper side of the display area ( Fig. 15 pads are in the upper portion of the substrate ), wherein the first part ( Fig. 15 vertical bus lines 1030 ) is disposed in the non-display area ( Fig. 15 left or right of the pixels ) between the plurality of pad areas and the display area ( Fig. 15 cell 1020 ) or in the non-display area opposite to the plurality of pad areas, and wherein the second part ( Fig. 15 final portions connecting the bus lines to the pads ) is disposed in the non-display area at left and right sides of the display area ( as shown in Fig. 15 ).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention, to utilize the teachings of Kim with Nam to implement the plurality of pad areas is positioned at an upper side of the display area, wherein the first part is disposed in the non-display area between the plurality of pad areas and the display area or in the non-display area opposite to the plurality of pad areas, and wherein the second part is disposed in the non-display area at left and right sides of the display area because this approach ensures easy electrical connection and inspection access.
Claim 15: Nam and Kim disclose the display device of claim 2 ( as discussed above ).
Nam teaches different voltages ( Fig. 3: VL3, and VL4 ) are applied to the first part ( [0078] the third voltage lines VL3 and the fourth voltage lines VL4 may be formed of the third conductive layer ), which is disposed in the non-display area ( Fig. 3: NDA ) between the plurality of pad areas ( Fig. 3 WPD_SC, WPD_DT, WPD_Vint, WPD_VL2 and WPD_VL1 ) and the display area ( Fig. 3: DPA), and the first parts ( as discussed above ) , which is disposed in the non-display area ( Fig. 3 NDA ) opposite to the plurality of pad areas ( Fig. 3: PDA).
Claims 5 and 7-9 are rejected under U.S.C. 103 as being unpatentable over Nam et al.; US 2023/0369345 A1; 12/2022 in view of Shima et al; US 2024/0334736 A1; 06/2022
Claim 5: Nam discloses the display device of claim 4 ( as discussed above ), wherein the first part ( [0079] the second voltage lines VL2 may be connected (e.g., electrically connected) to one or more wire pads WPD) is made of the same material ( [0078] The first voltage lines VL1 and the second voltage lines VL2 may be formed of the first conductive layer ) as the plurality of first assembling lines ( [0172] The first auxiliary electrodes FE1 and the second auxiliary electrode FE2 may include a transparent conductive material. The transparent conductive material may include amorphous indium tin oxide (ITO), crystalline ITO, amorphous indium zinc oxide (IZO), and crystalline IZO ) and the plurality of second assembling lines ( as discussed above ).
Nam does not appear to disclose the second part comprises: a first layer made of the same material as the light-blocking layer; and a second layer connected in parallel to the first layer and made of the same material as the source electrode and the drain electrode.
However, Shima teaches the second part comprises: a first layer ( Fig. 2A: 151 ) made of the same material as the light-blocking layer ( [0102] the light-blocking body may replace the auxiliary wiring and the arrangement of the light-blocking body can also be understood by referring to FIG. 1C ); and a second layer connected in parallel to the first layer ( Fig. 2B 151b; [0128] A conductive material having a light-transmitting property is preferably used for a second auxiliary wiring 151b positioned over the first auxiliary wiring 151a ) and made of the same material as the source electrode and the drain electrode ( [0281] For the conductive layer 161, one or two or more of metal materials selected from aluminum, titanium, chromium, manganese, iron, cobalt, nickel, copper, gallium, zinc, indium, tin, molybdenum, tantalum, tungsten, palladium, gold, platinum, silver, yttrium, and neodymium; an alloy combining these as appropriate; and the like can be used ).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention, to utilize the teachings of Sima with Nam to implement the second part comprises: a first layer made of the same material as the light-blocking layer; and a second layer connected in parallel to the first layer and made of the same material as the source electrode and the drain electrode because a two layer structure is a compact integrated design that combines optical blocking with electrical functionality in a single material system.
Claim 7: Nam and Shima disclose the display device of claim 5 ( as discussed above ).
Nam does not appear to disclose the first layer is disposed on an entire area of the second part, and the second layer is disposed only at a left or right side of the display area.
However, Shima teaches the first layer ( Fig. 2A: auxiliary wiring 151 ) is disposed on an entire area of the second part ( [0137] The auxiliary wiring 151 can be provided in the connection portion 140 as well as in the pixel portion 103 ), and the second layer ( Fig. 2B 151b ) is disposed only at a left or right side of the display area ( as shown in Fig. 15C ).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention, to utilize the teachings of Sima with Nam to implement the first layer is disposed on an entire area of the second part, and the second layer is disposed only at a left or right side of the display area because this approach balances environmental protection, electrical and optical uniformity, and interface control.
Claim 8: Nam and Shima disclose the display device of claim 5 ( as discussed above).
Nam teaches the plurality of first assembling lines ( Fig. 7 first auxiliary electrodes FE1 ) is each connected to the first part of each of the plurality of low-potential power link lines ( [0195] the first auxiliary electrodes FE1 may be connected (e.g., electrically connected) to electrode layers 117 or second semiconductor layers 113 of the light-emitting elements ED, and the second auxiliary electrode FE2 may be connected (e.g., electrically connected) to first semiconductor layers 111 of the light-emitting elements ED ) disposed in the non-display area ( as shown in Fig. 7 ) between the plurality of pad areas ( Fig. 3: PDA ) and the display area ( Fig. 3: DPA ) , wherein the plurality of second assembling lines ( Fig. 7 second auxiliary electrodes FE2 ) is each connected to the first part of each of the plurality of low-potential power link lines ( Fig. 5: VL2 ) disposed in the non-display area ( Fig. 3: NDA ) opposite to the plurality of pad areas ( Fig 3: PDA ), and wherein the plurality of first assembling lines ( Fig. 7: FE1 ) and the plurality of second assembling lines ( Fig. 7: FE2 ) are alternately disposed in the display area ( Fig. 3: DPA ).
Claim 9: Nam and Shima disclose the display device of claim 8 ( as discussed above).
Nam teaches one of the plurality of first assembling lines ( Fig. 7: FE1 ) and one of the plurality of second assembling lines ( Fig. 7 FE2 ) are connected to the same light-emitting element among the plurality of light-emitting elements ( Fig. 7: SPX1, SPX2, and SPX3 ).
Claim 6 is rejected under U.S.C. 103 as being unpatentable over Nam et al.; US 2023/0369345 A1; 12/2022 in view of Shima et al; US 2024/0334736 A1; 06/2022 as it relates to claim 5 above and further in view of Yu et al.; US 2024/0192810 A1; 07/2022
Claim 6: Nam and Shima disclose the display device of claim 5 ( as discussed above ).
Neither Nam nor Shima appear to disclose some of the plurality of first assembling lines each comprise a jumping pattern disposed in an area in which some of the plurality of first assembling lines intersect another first assembling line, and wherein some of the plurality of second assembling lines each comprise a jumping pattern disposed in an area in which some of the plurality of second assembling lines intersect another second assembling line.
However, Yu teaches some of the plurality of first assembling lines ( Fig. 4 first sub auxiliary lines 4024) each comprise a jumping pattern ( connection shown in Fig. 4 ) disposed in an area in which some of the plurality of first assembling lines ( Fig. 4 #4024 ) intersect another first assembling line ( Fig. 4 shows #4024 lines intersecting ), and wherein some of the plurality of second assembling lines ( Fig. 4 second sub auxiliary lines 4025 ) each comprise a jumping pattern ( connection shown in Fig. 4 ) disposed in an area in which some of the plurality of second assembling lines ( Fig. 4 #4025 ) intersect another second assembling line ( as shown in Fig. 4 ).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention, to utilize the teachings of Yu with Nam and Shima to implement some of the plurality of first assembling lines each comprise a jumping pattern disposed in an area in which some of the plurality of first assembling lines intersect another first assembling line, and wherein some of the plurality of second assembling lines each comprise a jumping pattern disposed in an area in which some of the plurality of second assembling lines intersect another second assembling line because the jumping action is a deliberate layout and electrical strategy to prevent short circuits and reduce surface area and spacing constraints.
Claim 14 is rejected under U.S.C. 103 as being unpatentable over Nam et al.; US 2023/0369345 A1; 12/2022 in view of Lee et al.; US 12,652,888 B2; 03/2022
Claim 14: Nam discloses the display device of claim 1 ( as discussed above ).
Nam does not appear to disclose each of the plurality of low-potential power link lines is made of a metallic material.
However, Lee teaches each of the plurality of low-potential power link lines ( Col. 5 lines 25 – 28 the second driving power supply VSS may be set as a low-potential power supply ) is made of a metallic material ( Col. 15 lines 1-3 the second contact electrode CNE2 may include a material such as indium tin oxide (ITO), indium zinc oxide (IZO), or indium tin zinc oxide (ITZO)).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention, to utilize the teachings of Lee with Nam to implement each of the plurality of low-potential power link lines is made of a metallic material because this approach enables high electrical conductivity, low and uniform resistance, and crosstalk reduction.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to KIMBERLY N FREY whose telephone number is (571)272-5068. The examiner can normally be reached Monday - Friday 7:30 am - 5 pm.
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/K.N.F./Examiner, Art Unit 2817
/ALI NARAGHI/Primary Examiner, Art Unit 2817
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