DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Arguments
Applicant's arguments filed on 05/28/2026 have been fully considered but they are not persuasive. See rejection below using different BRI.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1-20 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Lee et al. 20220157690 (Lee).
PNG
media_image1.png
532
426
media_image1.png
Greyscale
Regarding claim 1, fig. 5 of Lee discloses an electronic device, comprising:
a first interconnect (middle 116 (copper – par [0047]/208);
a second interconnect (left 116 (copper)/208), wherein a lower portion of the first interconnect is laterally spaced apart from a lower portion of the second interconnect by an air gap 402; and
an insulating layer (layer 114/118/130/124 - silicon carbide or diamond – pa [0022]), disposed laterally between an upper portion of the first interconnect and an upper portion of the second interconnect;
wherein a thermal conductivity value (ki) of the insulating layer (silicon carbide or diamond) is greater than a thermal conductivity value (kc1) of the first interconnect (that of copper – as per applicant specification) and a thermal conductivity value (kc2) of the second interconnect (that of copper);
wherein a product of a thickness value (ti) of the insulating layer multiplying the thermal conductivity value (ki) of the insulating layer is equal to or greater than a product of a thickness value tci) of the first interconnect multiplying the thermal conductivity value (kc1) of the first interconnect (this is necessary the case and thickness of 114/118/130 > thickness of 116 and silicon carbide or diamond thermal conductivity value is greater than that of copper); and
wherein the product of the thickness value (ti) of the insulating layer multiplying the thermal conductivity value (ki) of the insulating layer is equal to or greater than a product of a thickness value (tc2) of the second interconnect multiplying the thermal conductivity value (kc2) of the second interconnect (this is necessary the case and thickness of 114/118/130 > thickness of 116 and silicon carbide or diamond thermal conductivity value is greater than that of copper), satisfying a mathematical relationship of:
ti x Ki > tc1 x kc1; and
ti x ki > tc2 x kc2.
Regarding claim 2, fig. 5 of wherein a top dimension (half of top surface) of the first interconnect is less than a bottom dimension (full bottom surface) of the first interconnect.
Regarding claim 3, fig. 5 of Lee discloses wherein a top surface of the insulating layer (top of 114) and a top surface of the first interconnect are coplanar, and the thickness value of the insulating layer is thinner than the thickness value of the first interconnect (thick of top 114 above 402 is thinner than 116).
Regarding claim 4, par [0022] of Lee discloses wherein a material of the insulating layer comprises (diamond, SiC).
Regarding claim 5, Lee discloses wherein a material of the first interconnect and the second interconnect comprises copper – par [0047].
Regarding claim 6, fig. 5 of Lee discloses wherein the first interconnect and the second interconnect are identical in thickness value.
Regarding claim 7, fig. 5 of Lee discloses further comprising: an insulating sustaining layer 114/402, extending from a sidewall of the upper portion of the first interconnect to a sidewall of the upper portion of the second interconnect.
Regarding claim 8, fig. 5 of Lee discloses comprising: a dielectric capping layer 118, extending from a sidewall of the first interconnect to a sidewall of the second interconnect, wherein the air gap is enclosed by a portion of the insulating sustaining layer and a portion of the dielectric capping layer.
Regarding claim 9, Lee discloses wherein a thermal conductivity value of the dielectric capping layer is greater than the thermal conductivity value of the first interconnect and the thermal conductivity value of the second interconnect, and the dielectric capping layer is thermal coupled to the first interconnect, the insulating layer and the second interconnect.
Regarding claim 10, fig. 5 of Lee discloses further comprising: an active device, wherein the first interconnect is electrically connected and thermal coupled to the active device.
Regarding claim 11, fig. 5 of Lee discloses wherein the first interconnect and the active device are structurally overlapped.
Regarding claim 12, fig. 5 of Lee discloses wherein the second interconnect is electrically insulated from the first interconnect.
Regarding claim 13, Lee discloses wherein the second interconnect is a dummy pattern (as it is not connected to active device).
Regarding claim 14, fig. 5 of Lee discloses an electronic device, comprising:
a substrate 102;
an interconnect 116, disposed on the substrate;
a first insulating layer 202, disposed on the substrate; and
a second insulating layer (layer 114/118/130/124 - silicon carbide or diamond – pa [0022]), disposed over the first insulating layer and surrounding the interconnect;
wherein a portion of the first insulating layer 202 is vertically spaced apart from a portion of the second insulating layer by an air gap 402;
wherein a thermal conductivity value (ki) of the second insulating layer is greater than a thermal conductivity value (kc) of the interconnect, and
wherein a product of a thickness value (ti) of the second insulating layer multiplying the thermal conductivity value (ki) of the second insulating layer is equal to or greater than a product of a thickness value (tc) of the interconnect multiplying the thermal conductivity value (kc) of the interconnect (this is necessary the case and thickness of 114/118/130 > thickness of 116 and silicon carbide or diamond thermal conductivity value is greater than that of copper),
satisfying a mathematical relationship of:
ti x ki >tc x kc.
Regarding claim 15, par [0022] of Lee discloses wherein a material of the second insulating layer comprises diamond or SiC.
Regarding claim 16, Lee discloses wherein a material of the interconnect comprises copper.
Regarding claim 17, fig. 5 of Lee discloses further comprising: an active device, disposed on the substrate, wherein the interconnect is electrically connected and thermal coupled to the active device, and the interconnect and the active device are structurally overlapped.
Regarding claim 18, Lee discloses a method, comprising:
providing a structure including a substrate 102 and at least one conductive layer 208 disposed on the substrate (fig. 11);
patterning the conductive layer to form interconnects 208 and at least one trench laterally between the interconnects (fig. 12);
forming a sacrificial layer 502 (fig. 17) in the at least one trench;
forming a first insulating layer (layer 114/118/130/124 - silicon carbide or diamond – pa [0022]) covering the at least one trench (fig. 25A); and
performing a removal process to remove at least a portion of the sacrificial layer and to form an air gap (fig. 19);
wherein a thermal conductivity value (ki) of the first insulating layer (silicon carbide or diamond) is greater than a thermal conductivity value (kc) of the interconnects (that of copper – as per applicant specification), and
wherein a product of a thickness value (ti – total thickness of114/118/130/124) of the first insulating layer multiplying the thermal conductivity value (ki) of the first insulating layer (that of 130) is equal to or greater than a product of a thickness value (tc) of the interconnects (copper) multiplying the thermal conductivity value (kc)of the interconnects, satisfying a mathematical relationship of:
ti x ki, > tc x kc.
Regarding claim 19, fig. 25A of Lee discloses wherein the first insulating layer comprises an insulating sustaining layer 118 disposed on the interconnects and the sacrificial layer, the method further comprising: forming a second insulating layer 126 disposed on the first insulating layer and laterally between the interconnects.
Regarding claim 20 (see rejection of claims 15-16 above), Lee discloses a material of the insulating layer comprises diamond or SiC, and wherein a material of the interconnects comprises copper.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to VONGSAVANH SENGDARA whose telephone number is (571)270-5770. The examiner can normally be reached 9AM-6PM EST.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, PURVIS A. Sue can be reached on (571 )272-1236. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/VONGSAVANH SENGDARA/ Primary Examiner, Art Unit 2893
Prosecution Insights