DETAILED ACTION
Election/Restrictions
Claims 2-4, 8-10, 12-14 are withdrawn from further consideration pursuant to 37 CFR 1.142(b) as being drawn to a nonelected species, there being no allowable generic or linking claim. Election was made without traverse in the reply filed on 04/29/2026.
Priority
Receipt is acknowledged of certified copies of papers required by 37 CFR 1.55.
Information Disclosure Statement
The information disclosure statements (IDS) submitted on 12/27/2023 and 03/05/2024 are in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statements are being considered by the examiner.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1, 5-7, 11 and 15 are rejected under 35 U.S.C. 103 as being unpatentable over FAN et al. (US 20190326329 A1), hereinafter “Fan,” in view of KUSUNOKI et al. (US 20200403028 A1), hereinafter “Kusunoki.”
Re: Claim 1, Fan discloses a display device (Fig. 1: electronic device 1; Fig. 2: electronic/display device 10; ¶0023: display device 1), comprising:
a substrate having a first area (Fig. 2: substrate 102);
a transistor located in the first area (Fig. 2: S/D regions 110a, channel region 110b and gate 114; ¶0054: active layer 110 may include source/drain regions 110a and a channel region 110b of a thin-film transistor);
a first conductive feature located over the transistor and electrically connected to a source/drain of the transistor (Fig. 2: conductive layer 142, i.e., first conductive feature is located over active region 110a/b which is electrically connected to the S/D 110a of the transistor; ¶0092: conductive layer 142 may include … titanium, aluminum, … alloys thereof, other applicable conductive materials, or a combination thereof), …
…
…
a conductive pad located on the first conductive feature (Fig. 2: conductive pads 146a/b on conductive layer 142, i.e., first conductive feature), electrically connected to the first conductive feature and at least comprising nickel and gold (Fig. 2: 146a/b electrically connected to 142; ¶0101: conductive pad 146a/b may include a stacking structure containing multiple metal layers (e.g., a Ni/Au stacking structure)); and
a light-emitting device located on the conductive pad and electrically connected to the conductive pad (Fig. 2: LED 150 on conductive pads 146a/b).
Fan discloses that the first conductive feature may include titanium, aluminum and combinations thereof (see ¶0092). However, while Fan also discloses that a conductive layer may include a stacking structure containing multiple metal layers (e.g., Ti/Al/Ti stacking structure) in ¶0079, Fan does not clearly show wherein the first conductive feature comprises:
a first protective layer having a first thickness and at least comprising titanium;
a first conductive layer located above the first protective layer, having a second thickness and at least comprising aluminum, wherein the second thickness is greater than the first thickness;
In a similar field of endeavor, Kusunoki discloses wherein the first conductive feature comprises (Fig. 1: conductive feature 184a and 184b; ¶0087: The plug preferably includes the conductive layer 184b in contact with the side surface of the opening and the top surface of one of the pair of conductive layers 166, and the conductive layer 184a embedded inside the conductive layer 184b. Here, a conductive material in which hydrogen and oxygen are less likely to be diffused is preferably used for the conductive layer 184b.):
a first protective layer having a first thickness and at least comprising titanium (Fig. 1: conductive layer 184b, i.e., first protective layer; ¶0091: Examples of material that can be used for the conductive layers include titanium);
a first conductive layer located above the first protective layer (¶0091: a two-layer structure in which an aluminum film, i.e., first conductive layer, is stacked over, i.e., above, a titanium film, i.e., first protective layer), having a second thickness and at least comprising aluminum (Fig. 1: conductive layer 184a, i.e., first conductive layer; ¶0091: Examples of material that can be used for the conductive layers include aluminum), wherein the second thickness is greater than the first thickness (Fig. 1 shows 184a which has a greater thickness than 184b; ¶0091: a two-layer structure in which an aluminum film is stacked over a titanium film);
Therefore, it would have been obvious to a person having ordinary skill in the art before the effective filing date of the current application to have modified the conductive feature disclosed in Fan with the conductive structure disclosed in Kusunoki in order to create a plug wherein hydrogen and oxygen are less likely to be diffused (See Kusunoki, ¶0087).
Re: Claim 5, the combination of Fan in view of Kusunoki discloses the display device of claim 1.
Fan also discloses further comprising: a first dielectric layer located on the substrate and having a first opening exposing a top surface of the first conductive feature (Fig. 2: insulating layer 144, i.e., first dielectric layer, has a first opening which exposes the top surface of conductive layer 142, i.e., first conductive feature; ¶0097: insulating layer 144 may include silicon nitride, silicon oxide, another applicable material), wherein the first dielectric layer electrically isolates the light-emitting device and the first conductive feature (Fig. 2: insulating/dielectric layer insulates LED 150 from conductive layer 142, i.e., first conductive feature),
the conductive pad fills the first opening and a top surface of the conductive pad is higher than a top surface of the first dielectric layer (Fig. 2: conductive pads 146a/b fill the first opening in insulating/dielectric layer 144, and a top surface of the conductive pad 146a/b is higher than a top surface of the first insulating/dielectric layer 144).
Re: Claim 6, the combination of Fan in view of Kusunoki discloses the display device of claim 5.
Fan also discloses further comprising: a second dielectric layer located between the first dielectric layer and the transistor (Fig. 2: insulating layer 136, i.e., second dielectric layer, is located between the first insulating/dielectric layer 144 and the active region 110a/b, i.e., transistor); and
a second conductive feature located over the transistor and covered by the second dielectric layer (Fig. 2: conductive line 134, i.e., second conductive feature, is located over active region 110a/b, i.e., transistor, and covered by the second insulating/dielectric layer 136), wherein the second conductive feature electrically connects the first conductive feature and the transistor (Fig. 2: second conductive line 134, i.e., second conductive feature, connects the first conductive feature 142 and the transistor S/D 110a),
wherein the second dielectric layer has a second opening in the first area exposing a top surface of the second conductive feature (Fig. 2: second insulating/dielectric layer 136 has a second opening, below the first opening in the first insulating/dielectric layer 144, which exposes a top surface of the second conductive layer/conductive feature 134),
…
However, Fan does not clearly show wherein the first protective layer conformally covers the top surface of the second conductive feature and a plurality of sidewalls of the second opening, and the first conductive layer fills the second opening
Kusunoki further shows where the first protective layer conformally covers the top surface of the second conductive feature and a plurality of sidewalls of the second opening (Fig. 2 shows a conductive layer 184b, i.e., first protective layer, which surrounds a conductive layer 184a. This layer was used to teach a modification to Fan’s first conductive layer/feature of Fig. 2. With this layer surrounding conductive layer 142 of Fan, then it would be the case that the first protective layer 184b of Kusunoki would conformally cover the top surface of the second conductive feature 134 as well as a plurality of sidewalls of the second opening.), and the first conductive layer fills the second opening (Fig. 2: conductive layer 184a, i.e., first conductive feature. This layer was used to teach a modification to Fan’s first conductive layer/feature of Fig. 2. With this modification it would be the case that the first conductive layer 142 would fill the second opening in Fan’s second opening within the insulating layer 136.; Furthermore, Fan discloses the following: ¶0079: the conductive layer 134 may include a stacking structure containing multiple metal layers (e.g., Ti/Al/Ti stacking structure).
Therefore, it would have been obvious to a person having ordinary skill in the art before the effective filing date of the current application to have modified the conductive feature disclosed in Fan with the conductive structure disclosed in Kusunoki in order to create a plug wherein hydrogen and oxygen are less likely to be diffused (See Kusunoki, ¶0087).
Re: Claim 7, the combination of Fan in view of Kusunoki discloses the display device of claim 6.
Fan further discloses wherein the second conductive feature further comprises (Fig. 2: conductive line 134, i.e., second conductive feature; ¶0079: the conductive layer 134 may include a stacking structure containing multiple metal layers (e.g., Ti/Al/Ti stacking structure):
However, Fan does not clearly disclose a second protective layer having the first thickness; and
a second conductive layer located on the second protective layer and having the second thickness, wherein the first protective layer of the first conductive feature directly contacts the second conductive layer of the second conductive feature.
Kusunoki further discloses a second protective layer having the first thickness (Fig. 1: conductive layer 184a, i.e., second protective layer, having a first thickness; ¶0091: Examples of material that can be used for the conductive layers include titanium); and
a second conductive layer located on the second protective layer and having the second thickness (¶0091: a two-layer structure in which an aluminum film, i.e., first conductive layer, is stacked over, i.e., above, a titanium film, i.e., first protective layer; Fig. 1: conductive layer 184a, i.e., second conductive layer, having a second thickness; ¶0091: Examples of material that can be used for the conductive layers include aluminum), wherein the first protective layer of the first conductive feature directly contacts the second conductive layer of the second conductive feature (Fig. 1 shows 184a which has a greater thickness than 184b; ¶0091: a two-layer structure in which an aluminum film is stacked over a titanium film).
Therefore, it would have been obvious to a person having ordinary skill in the art before the effective filing date of the current application to have modified the conductive feature disclosed in Fan with the conductive structure disclosed in Kusunoki in order to create a plug wherein hydrogen and oxygen are less likely to be diffused (See Kusunoki, ¶0087).
Re: Claim 11, Fan discloses a display device (Fig. 1: electronic device 1; Fig. 2: electronic/display device 10; ¶0023: display device 1), comprising:
a substrate having a first area (Fig. 2: substrate 102);
a transistor located in the first area (Fig. 2: S/D regions 110a, channel region 110b and gate 114; ¶0054: active layer 110 may include source/drain regions 110a and a channel region 110b of a thin-film transistor);
a first conductive feature located over the transistor and electrically connected to a source/drain of the transistor (Fig. 2: conductive layer 142, i.e., first conductive feature is located over active region 110a/b which is electrically connected to the S/D 110a of the transistor; ¶0092: conductive layer 142 may include … titanium, aluminum, … alloys thereof, other applicable conductive materials, or a combination thereof), …
…
…
a first dielectric layer located on the substrate and having a first opening exposing a top surface of the first conductive feature (Fig. 2: insulating layer 144, i.e., first dielectric layer, has a first opening which exposes the top surface of conductive layer 142, i.e., first conductive feature; ¶0097: insulating layer 144 may include silicon nitride, silicon oxide, another applicable material); and
a conductive pad located on the first conductive feature (Fig. 2: conductive pads 146a/b on conductive layer 142, i.e., first conductive feature), electrically connected to the first conductive feature and at least comprising nickel and gold (Fig. 2: 146a/b electrically connected to 142; ¶0101: conductive pad 146a/b may include a stacking structure containing multiple metal layers (e.g., a Ni/Au stacking structure)).
Fan discloses that the first conductive feature may include titanium, aluminum and combinations thereof (see ¶0092). However, while Fan also discloses that a conductive layer may include a stacking structure containing multiple metal layers (e.g., Ti/Al/Ti stacking structure) in ¶0079, Fan does not clearly show wherein the first conductive feature comprises:
a first protective layer having a first thickness and at least comprising titanium;
a first conductive layer located above the first protective layer, having a second thickness and at least comprising aluminum, wherein the second thickness is greater than the first thickness;
In a similar field of endeavor, Kusunoki discloses wherein the first conductive feature comprises (Fig. 1: conductive feature 184a and 184b; ¶0087: The plug preferably includes the conductive layer 184b in contact with the side surface of the opening and the top surface of one of the pair of conductive layers 166, and the conductive layer 184a embedded inside the conductive layer 184b. Here, a conductive material in which hydrogen and oxygen are less likely to be diffused is preferably used for the conductive layer 184b.):
a first protective layer having a first thickness and at least comprising titanium (Fig. 1: conductive layer 184b, i.e., first protective layer; ¶0091: Examples of material that can be used for the conductive layers include titanium);
a first conductive layer located above the first protective layer (¶0091: a two-layer structure in which an aluminum film, i.e., first conductive layer, is stacked over, i.e., above, a titanium film, i.e., first protective layer), having a second thickness and at least comprising aluminum (Fig. 1: conductive layer 184a, i.e., first conductive layer; ¶0091: Examples of material that can be used for the conductive layers include aluminum), wherein the second thickness is greater than the first thickness (Fig. 1 shows 184a which has a greater thickness than 184b; ¶0091: a two-layer structure in which an aluminum film is stacked over a titanium film);
Therefore, it would have been obvious to a person having ordinary skill in the art before the effective filing date of the current application to have modified the conductive feature disclosed in Fan with the conductive structure disclosed in Kusunoki in order to create a plug wherein hydrogen and oxygen are less likely to be diffused (See Kusunoki, ¶0087).
Re: Claim 15, the combination of Fan in view of Kusunoki discloses the display device of claim 11.
Fan also discloses further comprising: a second dielectric layer located between the first dielectric layer and the transistor (Fig. 2: insulating layer 136, i.e., second dielectric layer, is located between the first insulating/dielectric layer 144 and the active region 110a/b, i.e., transistor); and
a second conductive feature located over the transistor and covered by the second dielectric layer (Fig. 2: conductive line 134, i.e., second conductive feature, is located over active region 110a/b, i.e., transistor),
wherein the second conductive feature electrically connects the first conductive feature and the transistor (Fig. 2: second conductive line 134, i.e., second conductive feature, electrically connects the first conductive feature 142 and the transistor S/D 110a),
wherein the second dielectric layer has a second opening in the first area exposing a top surface of the second conductive feature (Fig. 2: second insulating/dielectric layer 136 has a second opening, below the first opening in the first insulating/dielectric layer 144, which exposes a top surface of the second conductive layer/conductive feature 134),
…
However, Fan does not clearly show wherein the first protective layer conformally covers the top surface of the second conductive feature and a plurality of sidewalls of the second opening, and the first conductive layer fills the second opening.
Kusunoki further shows wherein the first protective layer conformally covers the top surface of the second conductive feature and a plurality of sidewalls of the second opening (Fig. 1 shows a conductive layer 184b, i.e., first protective layer, which surrounds a conductive layer 184a. This layer was used to teach a modification to Fan’s first conductive layer/feature of Fig. 1. With this layer surrounding conductive layer 142 of Fan, then it would be the case that the first protective layer 184b of Kusunoki would conformally cover the top surface of the second conductive feature 134 as well as a plurality of sidewalls of the second opening.), and the first conductive layer fills the second opening (Fig. 1: conductive layer 184a, i.e., first conductive feature. This layer was used to teach a modification to Fan’s first conductive layer/feature of Fig. 2. With this modification it would be the case that the first conductive layer 142 would fill the second opening in Fan’s second opening within the insulating layer 136.; Furthermore, Fan discloses the following: ¶0079: the conductive layer 134 may include a stacking structure containing multiple metal layers (e.g., Ti/Al/Ti stacking structure).
Therefore, it would have been obvious to a person having ordinary skill in the art before the effective filing date of the current application to have modified the conductive feature disclosed in Fan with the conductive structure disclosed in Kusunoki in order to create a plug wherein hydrogen and oxygen are less likely to be diffused (See Kusunoki, ¶0087).
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure:
KOO et al. (US 20230413625 A1) – Fig. 3 discloses a display device structure relevant to currently claimed features.
ROBIN et al. (US 20230378236 A1) – Fig. 1A discloses a display device structure relevant to currently claimed features.
BAEK et al. (US 20210091161 A1) – Fig. 5 discloses a display device structure relevant to currently claimed features.
CHEN et al. (US 20140061924 A1) – Figs. 1 and 17 disclose interconnect structure relevant to currently claimed features.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to WILLIAM ADROVEL whose telephone number is (571)272-3048. The examiner can normally be reached 7:30 AM - 5:00 PM.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, LEONARD CHANG can be reached at (571) 270-3691. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/WILLIAM ADROVEL/Examiner, Art Unit 2898
/Leonard Chang/Supervisory Patent Examiner, Art Unit 2898
Prosecution Insights