DETAILED ACTION This office action is in response to the application filed on December 27 , 202 3 . The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA. Information Disclosure Statement The information disclosure statements (IDS) submitted on 1 2 / 2 7 /202 3 are being considered by the examiner. Claim Rejections - 35 USC § 102 In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status. The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action: A person shall be entitled to a patent unless – (a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention. (a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention. Claims 1- 2 , 11 are rejected under 35 U.S.C. 102(a)( 2 ) as being anticipated by S eo (US 202 3 / 0307371 ). With respect to Claim 1 , S eo shows (Fig. 4 , 6A-6B, 9-10 ) all aspects of the current invention including a semiconductor device comprising: a substrate (200) a stack structure (CELL) on an upper surface of the substrate, wherein the stack structure includes gate electrodes (WL21 – WL2n) and insulating layers (115) alternately stacked in a vertical direction that is perpendicular to the upper surface of the substrate and has a stepped structure in a cross-sectional view; a gate pad (CP 2 ) on the stack structure; a first through via ( via 172 b; Fig 10 shows enlarged S3 region ) that extends through the stack structure in the vertical direction; a second through via ( via 172a; Fig 6A-6B shows enlarged S2 region ) that is spaced apart from the first through via in a horizontal direction that is parallel to the upper surface of the substrate, wherein the second through via extends through the stack structure in the vertical direction, wherein the second through via is electrically connected to a first gate electrode (uppermost) that is farthest one among the gate electrodes from the upper surface of the substrate in the vertical direction, wherein the gate pad is on the first gate electrode and is in contact with the first gate electrode, wherein the first through via includes: a vertical pattern (172b) ; a first protrusion ( protrusion 176 in region R21) that protrudes from the vertical pattern, wherein the first protrusion extends in the horizontal direction and overlaps at least a portion of the first gate electrode in the horizontal direction; a second protrusion (protrusion 176 in region R12) that protrudes from the vertical pattern, wherein the second protrusion extends in the horizontal direction and overlaps a second gate electrode in the horizontal direction, wherein the second gate electrode is between the first gate electrode and the upper surface of the substrate and spaced apart from the second through via With respect to Claim 2 , Seo shows (Fig. 4,9-10) wherein the first protrusion and the second protrusion have sidewalls recessed inward toward the vertical pattern With respect to Claim 11 , Seo shows (Fig. 4, 6A-6B, 9-10) further comprising: a circuit transistor (PT) on the substrate; a wiring structure (PERI) on the substrate, wherein the wiring structure is electrically connected to the circuit transistor; an interlayer insulating layer (140) on the substrate, wherein the interlayer insulating layer is on the circuit transistor and the wiring structure; and a common source plate (102) on the interlayer insulating layer, wherein the gate electrodes are on the common source plate, and the second through via (via 172a) passes through the common source plate to be electrically connected to the wiring structure . Claims 1 -4, 6-7, 10- 1 5 are rejected under 35 U.S.C. 102(a)( 1 ) as being anticipated by Kim (US 2021/0193672) With respect to Claim 1 , Kim shows (Fig. 10-11, 30-3 4 ) all aspects of the current invention including a semiconductor device comprising : a substrate (100) a stack structure on an upper surface of the substrate, wherein the stack structure includes gate electrodes (572/574/576) and insulating layers (310) alternately stacked in a vertical direction that is perpendicular to the upper surface of the substrate and has a stepped structure in a cross-sectional view; a gate pad (577) on the stack structure; a first through via ( via 622) that extends through the stack structure in the vertical direction; a second through via (via 626) that is spaced apart from the first through via in a horizontal direction that is parallel to the upper surface of the substrate, wherein the second through via extends through the stack structure in the vertical direction, wherein the second through via is electrically connected to a first gate electrode that is farthest one among the gate electrodes from the upper surface of the substrate in the vertical direction, wherein the gate pad is on the first gate electrode and is in contact with the first gate electrode, wherein the first through via includes: a vertical pattern ( 622a ) ; a first protrusion ( 460 in upper opening 4 3 0 ) that protrudes from the vertical pattern, wherein the first protrusion extends in the horizontal direction and overlaps at least a portion of the first gate electrode in the horizontal direction; a second protrusion ( 460 in lower opening 430 ) that protrudes from the vertical pattern, wherein the second protrusion extends in the horizontal direction and overlaps a second gate electrode in the horizontal direction, wherein the second gate electrode is between the first gate electrode and the upper surface of the substrate and spaced apart from the second through via With respect to Claim 2 , Kim shows (Fig. 10-11, 30-34) wherein the first protrusion and the second protrusion have sidewalls recessed inward toward the vertical pattern With respect to Claim 3 , Kim shows (Fig. 10-11, 30-34) further comprising: a first insulating pattern (560) between the first protrusion and a sidewall of the first gate electrode that faces the first protrusion; and a second insulating pattern (560) between the second protrusion and a sidewall of the second gate electrode With respect to Claim 4 , Kim shows (Fig. 10-11, 30-34) wherein at least a portion of the first protrusion overlaps the first insulating pattern in the horizontal direction, and the second protrusion overlaps the second insulating pattern in the horizontal direction . With respect to Claim 6 , Kim shows (Fig. 10-11, 30-34) wherein the gate pad includes a pad portion (575) and a pad protrusion (opening 440) , wherein the pad portion extends in the horizontal direction, and wherein the pad protrusion protrudes from the pad portion and extends in the vertical direction. With respect to Claim 7 , Kim shows (Fig. 10-11, 30-34) wherein the pad protrusion extends around a sidewall of the second through vi a. With respect to Claim 10 , Kim shows (Fig. 10-11, 30-34) wherein, from a plan view, the first through via and the second through via are alternately arranged in the horizontal direction With respect to Claim 11 , Kim shows (Fig. 10-11, 30-34) further comprising: a circuit transistor (156) on the substrate; a wiring structure (206,216,226) on the substrate, wherein the wiring structure is electrically connected to the circuit transistor; an interlayer insulating layer (340) on the substrate, wherein the interlayer insulating layer is on the circuit transistor and the wiring structure; and a common source plate (240) on the interlayer insulating layer, wherein the gate electrodes are on the common source plate, and the second through via (via 626) passes through the common source plate to be electrically connected to the wiring structure . With respect to Claim 12 , Kim shows (Fig. 10-11, 30-34) all aspects of the current invention including a semiconductor device comprising: a substrate (100) a stack structure on an upper surface of the substrate, wherein the stack structure includes gate electrodes (572/574/576) and insulating layers (310) alternately stacked in a vertical direction that is perpendicular to the upper surface of the substrate and has a stepped structure in a cross-sectional view; a gate pad (577) on the stack structure; a first through via (via 622 ) that extends through the stack structure in the vertical direction; wherein the first through via includes a first insulating material ( 460 ) a second through via (via 626) that is spaced apart from the first through via in a horizontal direction that is parallel to the upper surface of the substrate, wherein the second through via extends through the stack structure in the vertical direction, wherein the second through via is electrically connected to a first gate electrode that is farthest one among the gate electrodes from the upper surface of the substrate in the vertical direction ; a vertical structure (590) that is spaced apart from the first through via and the second through via, wherein the vertical structure extends through the stack structure in the vertical direction and includes a second insulating material wherein the gate pad is on the first gate electrode and is in contact with the first gate electrode wherein the first through via includes: a vertical pattern (622a) ; a first protrusion (460 in upper opening 430) that protrudes from the vertical pattern, wherein the first protrusion extends in the horizontal direction and overlaps at least a portion of the first gate electrode in the horizontal direction; a second protrusion (460 in lower opening 430) that protrudes from the vertical pattern, wherein the second protrusion extends in the horizontal direction and overlaps a second gate electrode in the horizontal direction, wherein the second gate electrode is between the first gate electrode and the upper surface of the substrate and spaced apart from the second through via With respect to Claim 13 , Kim shows (Fig. 10-11, 30-34) wherein the first protrusion and the second protrusion have sidewalls recessed inward toward the vertical pattern With respect to Claim 14 , Kim shows (Fig. 10-11, 30-34) further comprising: a first insulating pattern (560) between the first protrusion and a sidewall of the first gate electrode that faces the first protrusion; and a second insulating pattern (560) between the second protrusion and a sidewall of the second gate electrode With respect to Claim 15 , Kim shows (Fig. 10-11, 30-34) wherein a lower surface of the first through via and a lower surface of the vertical structure are located at an equal vertical distance from the upper surface of the substrate . Claim 12 is rejected under 35 U.S.C. 102(a)( 1 ) as being anticipated by Seo (US 2021/0375920). With respect to Claim 12 , Seo shows (Fig. 4, 10, 12-13) all aspects of the current invention including a semiconductor device comprising: a substrate (4) a stack structure (46) on an upper surface of the substrate, wherein the stack structure includes gate electrodes (44) and insulating layers (48) alternately stacked in a vertical direction that is perpendicular to the upper surface of the substrate and has a stepped structure in a cross-sectional view; a gate pad (51p) on the stack structure; a first through via (via 86 ) that extends through the stack structure in the vertical direction; wherein the first through via includes a first insulating material ( 85 ) a second through via (via 92 ) that is spaced apart from the first through via in a horizontal direction that is parallel to the upper surface of the substrate, wherein the second through via extends through the stack structure in the vertical direction, wherein the second through via is electrically connected to a first gate electrode (uppermost) that is farthest one among the gate electrodes from the upper surface of the substrate in the vertical direction ; a vertical structure ( 54 ) that is spaced apart from the first through via and the second through via, wherein the vertical structure extends through the stack structure in the vertical direction and includes a second insulating material wherein the gate pad is on the first gate electrode and is in contact with the first gate electrode wherein the first through via includes: a vertical pattern (middle portion 85) ; a first protrusion (upper protrusion 85) that protrudes from the vertical pattern, wherein the first protrusion extends in the horizontal direction and overlaps at least a portion of the first gate electrode in the horizontal direction; a second protrusion (lower protrusion 85) that protrudes from the vertical pattern, wherein the second protrusion extends in the horizontal direction and overlaps a second gate electrode in the horizontal direction, wherein the second gate electrode is between the first gate electrode and the upper surface of the substrate and spaced apart from the second through via Claims 18-1 9 are rejected under 35 U.S.C. 102(a)( 2 ) as being anticipated by Seo (US 2023/0307371). With respect to Claim 18 , Seo shows (Fig. 4, 6A-6B, 9-10) all aspects of the current invention including an electronic system comprising : a first substrate ( 2001 ) a semiconductor device (2003) on the first substrate; a controller (2002) electrically connected to the semiconductor device on the first substrate, wherein the semiconductor device includes : a second substrate (200) a stack structure (CELL) on an upper surface of the substrate, wherein the stack structure includes gate electrodes (WL21 – WL2n) and insulating layers (115) alternately stacked in a vertical direction that is perpendicular to the upper surface of the substrate and has a stepped structure in a cross-sectional view; a gate pad (CP2) on the stack structure; a first through via (via 172b; Fig 10 shows enlarged S3 region) that extends through the stack structure in the vertical direction; a second through via (via 172a; Fig 6A-6B shows enlarged S2 region) that is spaced apart from the first through via in a horizontal direction that is parallel to the upper surface of the substrate, wherein the second through via extends through the stack structure in the vertical direction, wherein the second through via is electrically connected to a first gate electrode (uppermost) that is farthest one among the gate electrodes from the upper surface of the substrate in the vertical direction, wherein the gate pad is on the first gate electrode and is in contact with the first gate electrode, wherein the first through via includes: a vertical pattern (172b) ; a first protrusion (protrusion 176 in region R21) that protrudes from the vertical pattern, wherein the first protrusion extends in the horizontal direction and overlaps at least a portion of the first gate electrode in the horizontal direction; a second protrusion (protrusion 176 in region R12) that protrudes from the vertical pattern, wherein the second protrusion extends in the horizontal direction and overlaps a second gate electrode in the horizontal direction, wherein the second gate electrode is between the first gate electrode and the upper surface of the substrate and spaced apart from the second through via With respect to Claim 19 , Seo shows (Fig. 4,9-10) wherein the first protrusion and the second protrusion have sidewalls recessed inward toward the vertical pattern Claim Rejections - 35 USC § 103 In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status. This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention. The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action: A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made. Claim 5 is rejected under 35 U.S.C. 103 as being unpatentable over Kim (US 2021/0193672) . With respect to Claim 5 , Kim shows (Fig. 10-11, 30-34) most aspects of the current invention including a first insulating pattern (560) between the first protrusion and a sidewall of the first gate electrode that faces the first protrusion; and a second insulating pattern (560) between the second protrusion and a sidewall of the second gate electrode and further wherein the first insulating pattern has a first thickness in the vertical direction, and the second insulating pattern has a second thickness in the vertical direction , wherein the second thickness is equal to the first thickness . Regarding claim 5 , the courts have held that differences in the thicknesses will not support the patentability of subject matter encompassed by the prior art unless there is evidence indicating such thicknesses are critical. “Where the general conditions of a claim are disclosed in the prior art, it is not inventive to discover the workable ranges by routine experimentation.” See In re Aller, 220 F.2d 454, 456, 105, USPQ 233, 235 (CCPA 1955 ). Since the applicant has not established the criticality of the thicknesses and similar thicknesses are known in the art (see e.g. Kim ), it would have been obvious to one of the ordinary skill in the art to use these values in the device . Criticality: The specification contains no disclosure of either the critical nature of the claimed thicknesses or any unexpected results arising therefrom. Where patentability is said to be based upon particular chosen dimensions or upon another variable recited in a claim, the applicant must show that the chosen dimensions are critical. In re Woodruff, 919 F.2d 1575, 1578, 16 USPQ 2d 1934, 1936 (Fed Cir. 1990 ). Claims 18 -2 0 are rejected under 35 U.S.C. 103 as being unpatentable over Lim (US 2022/0189876) in view of Kim (US 2021/0193672). With respect to Claim 18 , Lim shows (Fig. 22,24) most aspects of the current invention including an electronic system comprising : a first substrate (2001) a semiconductor device (2003) on the first substrate; a controller (2002) electrically connected to the semiconductor device on the first substrate, wherein the semiconductor device includes : a second substrate (200) a stack structure (MS1/MS2) on an upper surface of the substrate, wherein the stack structure includes gate electrodes (WL1 – WL2n) and insulating layers (110) alternately stacked in a vertical direction that is perpendicular to the upper surface of the substrate and has a stepped structure in a cross-sectional view However, Lim does not show wherein the semiconductor device includes a gate pad on the stack structure; a first through via that extends through the stack structure in the vertical direction; and a second through via that is spaced apart from the first through via in a horizontal direction that is parallel to the upper surface of the second substrate, wherein the second through via extends through the stack structure in the vertical direction, wherein the second through via is electrically connected to a first gate electrode that is farthest one among the gate electrodes from the upper surface of the second substrate in the vertical direction, wherein the gate pad is on the first gate electrode and is in contact with the first gate electrode, and wherein the first through via includes: a vertical pattern; a first protrusion that protrudes from the vertical pattern, wherein the first protrusion extends in the horizontal direction and overlaps at least a portion of the first gate electrode in the horizontal direction; and a second protrusion that protrudes from the vertical pattern, wherein the second protrusion extends in the horizontal direction and overlaps a second gate electrode in the horizontal direction, wherein the second gate electrode is between the first gate electrode and the upper surface of the second substrate and spaced apart from the second through via. On the other hand, and in the same field of endeavor , Kim teaches (Fig. 10-11, 30-34) a semiconductor device includes : a substrate (100) a stack structure on an upper surface of the substrate, wherein the stack structure includes gate electrodes (572/574/576) and insulating layers (310) alternately stacked in a vertical direction that is perpendicular to the upper surface of the substrate and has a stepped structure in a cross-sectional view; a gate pad (577) on the stack structure; a first through via ( via 622) that extends through the stack structure in the vertical direction; a second through via (via 626) that is spaced apart from the first through via in a horizontal direction that is parallel to the upper surface of the substrate, wherein the second through via extends through the stack structure in the vertical direction, wherein the second through via is electrically connected to a first gate electrode that is farthest one among the gate electrodes from the upper surface of the substrate in the vertical direction, wherein the gate pad is on the first gate electrode and is in contact with the first gate electrode, wherein the first through via includes: a vertical pattern (622a) ; a first protrusion (460 in upper opening 430) that protrudes from the vertical pattern, wherein the first protrusion extends in the horizontal direction and overlaps at least a portion of the first gate electrode in the horizontal direction; a second protrusion (460 in lower opening 430) that protrudes from the vertical pattern, wherein the second protrusion extends in the horizontal direction and overlaps a second gate electrode in the horizontal direction, wherein the second gate electrode is between the first gate electrode and the upper surface of the substrate and spaced apart from the second through via Kim teaches forming insulation structures between the first conductive through via and sidewalls of each of the second gate electrodes, to electrically insulate the first conductive through via from each of the second gate electrodes and further allowing the first conductive through via to receive electrical signals from the lower wiring, so that there is no need to form an upper wiring to apply electrical signals to the first conductive through via . Therefore, it would have been obvious to one of ordinary skill in the art, and before the effective filing date of the claimed invention to have wherein the semiconductor device includes a gate pad on the stack structure; a first through via that extends through the stack structure in the vertical direction; and a second through via that is spaced apart from the first through via in a horizontal direction that is parallel to the upper surface of the second substrate, wherein the second through via extends through the stack structure in the vertical direction, wherein the second through via is electrically connected to a first gate electrode that is farthest one among the gate electrodes from the upper surface of the second substrate in the vertical direction, wherein the gate pad is on the first gate electrode and is in contact with the first gate electrode, and wherein the first through via includes: a vertical pattern; a first protrusion that protrudes from the vertical pattern, wherein the first protrusion extends in the horizontal direction and overlaps at least a portion of the first gate electrode in the horizontal direction; and a second protrusion that protrudes from the vertical pattern, wherein the second protrusion extends in the horizontal direction and overlaps a second gate electrode in the horizontal direction, wherein the second gate electrode is between the first gate electrode and the upper surface of the second substrate and spaced apart from the second through via in the device of Lim, as taught by Kim which allows forming insulation structures between the first conductive through via and sidewalls of each of the second gate electrodes, to electrically insulate the first conductive through via from each of the second gate electrodes and further allowing the first conductive through via to receive electrical signals from the lower wiring, so that there is no need to form an upper wiring to apply electrical signals to the first conductive through via . With respect to Claim 19 , Kim shows (Fig. 10-11, 30-34) wherein the first protrusion and the second protrusion have sidewalls recessed inward toward the vertical pattern With respect to Claim 20 , Kim shows (Fig. 10-11, 30-34) most aspects of the current invention including a first insulating pattern (560) between the first protrusion and a sidewall of the first gate electrode that faces the first protrusion; and a second insulating pattern (560) between the second protrusion and a sidewall of the second gate electrode and further wherein the first insulating pattern has a first thickness in the vertical direction, and the second insulating pattern has a second thickness in the vertical direction , wherein the second thickness is equal to the first thickness . Regarding claim 20 , the courts have held that differences in the thicknesses will not support the patentability of subject matter encompassed by the prior art unless there is evidence indicating such thicknesses are critical. “Where the general conditions of a claim are disclosed in the prior art, it is not inventive to discover the workable ranges by routine experimentation.” See In re Aller, 220 F.2d 454, 456, 105, USPQ 233, 235 (CCPA 1955 ). Since the applicant has not established the criticality of the thicknesses and similar thicknesses are known in the art (see e.g. Kim ), it would have been obvious to one of the ordinary skill in the art to use these values in the device of Lim in view of Kim. Criticality: The specification contains no disclosure of either the critical nature of the claimed thicknesses or any unexpected results arising therefrom. Where patentability is said to be based upon particular chosen dimensions or upon another variable recited in a claim, the applicant must show that the chosen dimensions are critical. In re Woodruff, 919 F.2d 1575, 1578, 16 USPQ 2d 1934, 1936 (Fed Cir. 1990 ) Allowable Subject Matter Claims 8-9 , 16-17 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims. Conclusion Any inquiry concerning this communication or earlier communications from the examiner should be directed to FILLIN "Examiner name" \* MERGEFORMAT QUINTON A BRASFIELD whose telephone number is FILLIN "Phone number" \* MERGEFORMAT (571)272-0804 . The examiner can normally be reached FILLIN "Work Schedule?" \* MERGEFORMAT M-F 9AM-4PM . Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. 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For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /Q.A.B/ Examiner, Art Unit 2814 /WAEL M FAHMY/ Supervisory Patent Examiner, Art Unit 2814