Notice of Pre-AIA or AIA Status The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA. Claim Rejections - 35 USC § 102 The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action: A person shall be entitled to a patent unless – (a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale , or otherwise available to the public before the effective filing date of the claimed invention. (a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention. Claims 1- 20 are rejected under 35 U.S.C. 102(a)(1) and (a)(2) as being anticipated by Huang et al. (US20230040094A1, hereinafter Huang ). Regarding claim 1 , Huang discloses a semiconductor structure that extends laterally with a first interconnect on one side and a second interconnect on an opposing side separated from the first interconnect by a longitudinal thickness of an insulating member that extends laterally along the first interconnect and the second interconnect (See below annotated fig. 1 lowest frontside layer M0 and first backside signal layer BM1 with an ILD within backside layer 150, substrate 130 , and an ILD within active device layer 110 having a longitudinal thickness between M0 and BM1) , the semiconductor structure comprising: a first source/drain (S/D) positioned in the insulating member between the first interconnect and the second interconnect (See below annotated fig. 1 first source/drain 122 positioned within substrate 130 and the ILD within active device layer 110) ; a second S/D positioned in the insulating member adjacent to the first S/D (See below annotated fig. 1 second source/drain 124 positioned within substrate 130 and the ILD within active device layer 110 adjacent to first source/drain 122) ; and 687070 1659255 0 0 a lead electrically connected to the first S/D and to the second interconnect, wherein a portion of the lead laps the first S/D and the second S/D laterally and is electrically insulated from the second S/D (See below annotated fig. 1 uppermost backside layer BM0 electrically connected to first S/D 122 and to first backside signal layer BM1 and a portion of BM0 overlaps first S/D 122 and second S/D 124 laterally and is electrically insulated from second S/D 124) . Regarding claim 2 , Huang discloses t he semiconductor structure of claim 1, further comprising a first rail that is electrically connected to the first S/D and to the second interconnect (See above annotated fig. 1 the rail connecting uppermost backside layer BM0 and first backside signal layer BM1 is electrically connected to first S/D 122 and first backside signal layer BM1) . Regarding claim 3 , Huang discloses t he semiconductor structure of claim 2, wherein the first rail is configured to supply electrical power to the first S/D (Par. 28 “ signals can be applied to the gates, as well as outputted from the sources/drains, through the backside metal layers BM0 and BM1 ”) . Regarding claim 4 , Huang discloses t he semiconductor structure of claim 2, further comprising a middle-of-line via electrically connected to the second S/D and to the first interconnect (See above annotated fig. 1 the middle-of-line via electrically connecting lowest frontside layer M0 and second S/D 124) . Regarding claim 5 , Huang discloses t he semiconductor structure of claim 2, further comprising a second rail that is electrically insulated from the first rail, wherein a first lateral distance between the first rail and the second rail is greater than a second lateral distance between the first S/D and the second S/D (See above annotated fig. 1 the second rail connecting uppermost backside layer BM0 and first backside signal layer BM1 is electrically insulated from the first rail by substrate 130 and the distance between the first and second rail is greater than a distance between the first and second S/Ds 122/124) . Regarding claim 6 , Huang discloses the semiconductor structure of claim 2, wherein the first rail laps the first S/D and the second S/D laterally ( F ig. 1 would reasonably disclose the rail connecting uppermost backside layer BM0 and first backside signal layer BM1 overlapping first and second S/Ds 122/124, see MPEP 2125.I). Regarding claim 7 , Huang discloses the semiconductor structure of claim 5, further comprising a third S/D and a fourth S/D (Fig. 3A illustrates a plurality of gates 320a-320d and so they teach multiple sets of S/D pair as depicted in fig. 1 depending on the given cross section) , wherein: the first S/D and the second S/D are spaced apart in a first direction (See above annotated fig. 1 first S/D 122 and second S/D 124 spaced apart in a first direction); the third S/D spaced apart from the first S/D in a second direction that is orthogonal to the first direction (Fig. 3A if the first and second S/Ds 122/124 are represented by gate 320a, then a third and fourth S/D 122/124 are represented by gate 320b which is spaced apart from the first and second S/Ds in a second direction perpendicular to the direction between first and second S/Ds) ; the fourth S/D spaced apart from the second S/D in the second direction (Fig. 3A if the first and second S/Ds 122/124 are represented by gate 320a, then a third and fourth S/D 122/124 are represented by gate 320b which is spaced apart from the first and second S/Ds in a second direction perpendicular to the direction between first and second S/Ds) ; and the fourth S/D is electrically connected to the first rail (See above annotated fig. 1 the rail connecting uppermost backside layer BM0 and first backside signal layer BM1 extends in a second direction and so it is also connected to fourth S/D 124) ; wherein the first rail laps the third S/D and the fourth S/D laterally ( F ig. 1 would reasonably disclose the rail connecting uppermost backside layer BM0 and first backside signal layer BM1 overlapping first and second S/Ds 122/124, see MPEP 2125.I). Regarding claim 8 , Huang discloses t he semiconductor structure of claim 2, wherein the first rail is centered and symmetric with respect to a cell border (See above annotated fig. 1 first rail lies central between first and second S/Ds 122/124) . Regarding claim 9 , Huang discloses t he semiconductor structure of claim 1, further comprising a via electrically connected to the second S/D and to the first interconnect, wherein the via is positioned on an opposite side of the second S/D from the lead (See above annotated fig. 1 the middle-of-line via electrically connecting lowest frontside layer M0 and second S/D 124) . Regarding claim 10 , Huang discloses t he semiconductor structure of claim 1, wherein the lead has an L-shape (See above annotated fig. 1 uppermost backside layer BM0 has an L-shape) . Regarding claim 11 , Huang discloses a semiconductor structure that extends laterally with a first interconnect on one side and a second interconnect on an opposing side separated from the first interconnect by a longitudinal thickness of an insulating member that extends laterally along the first interconnect and the second interconnect (See above annotated fig. 1 lowest frontside layer M0 and first backside signal layer BM1 with substrate 130 and an ILD within active device layer 110 having a longitudinal thickness between M0 and BM1) , the semiconductor structure comprising: a first source/drain (S/D) positioned in the insulating member between the first interconnect and the second interconnect (See above annotated fig. 1 first source/drain 122 positioned within substrate 130 and the ILD within active device layer 110) ; a lead electrically connected to the first S/D and to the second interconnect, wherein the lead has an L-shape (See above annotated fig. 1 uppermost backside layer BM0 electrically connected to first S/D 122 and to first backside signal layer BM1 and has an L-shape ) that comprises: a contact electrically connected to the first S/D that extends longitudinally from the first S/D towards the second interconnect (See above annotated fig. 1 uppermost backside layer BM0 has a portion in contact with first S/D 122); and an extension electrically connected to the contact that extends laterally across the second interconnect (See above annotated fig. 1 uppermost backside layer BM0 has a portion that extends laterally across first backside signal layer BM1 and is electrically connected to the above contact). Regarding claim 12 , Huang discloses the semiconductor structure of claim 11, wherein: the semiconductor structure further comprises a second S/D positioned in the insulating member adjacent to the first S/D (See above annotated fig. 1 second source/drain 124 positioned within substrate 130 and the ILD within active device layer 110 adjacent to first source/drain 122) ; and the extension laps the second S/D laterally and is electrically insulated from the second S/D (See above annotated fig. 1 a portion of BM0 overlaps second S/D 124 laterally and is electrically insulated from second S/D 124). Regarding claim 13 , Huang discloses the semiconductor structure of claim 11, wherein a width of the extension is at least twice a width of the contact ( F ig. 1 would reasonably disclose and suggest to a person of ordinary skill in the art the extension portion of BM0 having at least twice a width of the contact portion, see MPEP 2125.I). Regarding claim 14 , Huang discloses t he semiconductor structure of claim 11, further comprising a via electrically connected to the second S/D and to the first interconnect, wherein the contact is positioned on an opposite side of the second S/D from the lead (See above annotated fig. 1 the middle-of-line via electrically connecting lowest frontside layer M0 and second S/D 124). Regarding claim 15 , Huang discloses the semiconductor structure of claim 11, wherein: the insulating member comprises a plurality of insulators (See above annotated fig. 1 an ILD within backside layer 150, substrate 130 and an ILD within active device layer 110 comprise the insulating member); lateral sides of the contact are in direct contact with a first insulator of the plurality of insulators (See above annotated fig. 1 uppermost portion of uppermost backside layer BM0 in direct contact with substrate 130). Regarding claim 16 , Huang discloses t he semiconductor structure of claim 15, wherein lateral sides of the extension are in direct contact with a second insulator of the plurality of insulators that is different from the first insulator (See above annotated fig. 1 the extension portion of uppermost backside layer BM0 is in direct contact with the ILD within backside layer 150 which is different than substrate 130) . Regarding claim 17 , Huang discloses t he semiconductor structure of claim 11, further comprising a first rail that is electrically connected to the first S/D and to the second interconnect (See above annotated fig. 1 the rail connecting uppermost backside layer BM0 and first backside signal layer BM1 is electrically connected to first S/D 122 and first backside signal layer BM1), wherein the first rail laps the first S/D and the second S/D laterally ( F ig. 1 would reasonably disclose the rail connecting uppermost backside layer BM0 and first backside signal layer BM1 overlapping first and second S/Ds 122/124, see MPEP 2125.I). Regarding claim 18 , Huang discloses t he semiconductor structure of claim 11, wherein the first rail is centered and symmetric with respect to a cell border (See above annotated fig. 1 first rail lies central between first and second S/Ds 122/124). Regarding claim 19 , Huang discloses the semiconductor structure of claim 17, further comprising a third S/D and a fourth S/D (Fig. 3A illustrates a plurality of gates 320a-320d and so they teach multiple sets of S/D pair as depicted in fig. 1 depending on the given cross section) , wherein: the first S/D and the second S/D are spaced apart in a first direction (See above annotated fig. 1 first S/D 122 and second S/D 124 spaced apart in a first direction) ; the third S/D spaced apart from the first S/D in a second direction that is orthogonal to the first direction (Fig. 3A if the first and second S/Ds 122/124 are represented by gate 320a, then a third and fourth S/D 122/124 are represented by gate 320b which is spaced apart from the first and second S/Ds in a second direction perpendicular to the direction between first and second S/Ds) ; the fourth S/D spaced apart from the second S/D in the second direction (Fig. 3A if the first and second S/Ds 122/124 are represented by gate 320a, then a third and fourth S/D 122/124 are represented by gate 320b which is spaced apart from the first and second S/Ds in a second direction perpendicular to the direction between first and second S/Ds) ; and the fourth S/D is electrically connected to the first rail (See above annotated fig. 1 the rail connecting uppermost backside layer BM0 and first backside signal layer BM1 extends in a second direction and so it is also connected to fourth S/D 124) ; wherein the first rail laps the third S/D and the fourth S/D laterally (See above annotated fig. 1 while Huang does not explicitly disclose the rail connecting uppermost backside layer BM0 and first backside signal layer BM1, fig. 1 would reasonably disclose and suggest to a person of ordinary skill in the art wherein the first rail overlaps first and second S/Ds 122/124) . Regarding claim 20 , Huang discloses t he semiconductor structure of claim 11, wherein the lead has an L-shape (See above annotated fig. 1 uppermost backside layer BM0 has an L-shape) . Conclusion The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. Wang et al. ( US 2 0210305262A1 ) teaches a similar device to Huang’s. Any inquiry concerning this communication or earlier communications from the examiner should be directed to FILLIN "Examiner name" \* MERGEFORMAT COLE LEON LINDSEY whose telephone number is FILLIN "Phone number" \* MERGEFORMAT (571)272-4028 . The examiner can normally be reached FILLIN "Work Schedule?" \* MERGEFORMAT Monday - Friday, 8:00 a.m. - 5:00 p.m. . Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. 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