DETAILED ACTION Notice of Pre-AIA or AIA Status The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA. Information Disclosure Statement The information disclosure statement s (IDS) submitted on 05/13/2024, 10/28/2024 and 05/01/2025 w ere filed before the first action on the merits. The submission s are in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statement s are being considered by the examiner. Double Patenting The nonstatutory double patenting rejection is based on a judicially created doctrine grounded in public policy (a policy reflected in the statute) so as to prevent the unjustified or improper timewise extension of the “right to exclude” granted by a patent and to prevent possible harassment by multiple assignees. A nonstatutory double patenting rejection is appropriate where the conflicting claims are not identical, but at least one examined application claim is not patentably distinct from the reference claim(s) because the examined application claim is either anticipated by, or would have been obvious over, the reference claim(s). See, e.g., In re Berg , 140 F.3d 1428, 46 USPQ2d 1226 (Fed. Cir. 1998); In re Goodman , 11 F.3d 1046, 29 USPQ2d 2010 (Fed. Cir. 1993); In re Longi , 759 F.2d 887, 225 USPQ 645 (Fed. Cir. 1985); In re Van Ornum , 686 F.2d 937, 214 USPQ 761 (CCPA 1982); In re Vogel , 422 F.2d 438, 164 USPQ 619 (CCPA 1970); In re Thorington , 418 F.2d 528, 163 USPQ 644 (CCPA 1969). A timely filed terminal disclaimer in compliance with 37 CFR 1.321(c) or 1.321(d) may be used to overcome an actual or provisional rejection based on nonstatutory double patenting provided the reference application or patent either is shown to be commonly owned with the examined application, or claims an invention made as a result of activities undertaken within the scope of a joint research agreement. See MPEP § 717.02 for applications subject to examination under the first inventor to file provisions of the AIA as explained in MPEP § 2159. See MPEP § 2146 et seq. for applications not subject to examination under the first inventor to file provisions of the AIA. A terminal disclaimer must be signed in compliance with 37 CFR 1.321(b). The filing of a terminal disclaimer by itself is not a complete reply to a nonstatutory double patenting (NSDP) rejection. A complete reply requires that the terminal disclaimer be accompanied by a reply requesting reconsideration of the prior Office action. Even where the NSDP rejection is provisional the reply must be complete. See MPEP § 804, subsection I.B.1. For a reply to a non-final Office action, see 37 CFR 1.111(a). For a reply to final Office action, see 37 CFR 1.113(c). A request for reconsideration while not provided for in 37 CFR 1.113(c) may be filed after final for consideration. See MPEP §§ 706.07(e) and 714.13. The USPTO Internet website contains terminal disclaimer forms which may be used. Please visit www.uspto.gov/patent/patents-forms. The actual filing date of the application in which the form is filed determines what form (e.g., PTO/SB/25, PTO/SB/26, PTO/AIA/25, or PTO/AIA/26) should be used. A web-based eTerminal Disclaimer may be filled out completely online using web-screens. An eTerminal Disclaimer that meets all requirements is auto-processed and approved immediately upon submission. For more information about eTerminal Disclaimers, refer to www.uspto.gov/patents/apply/applying-online/eterminal-disclaimer . Claim s 1-7 are rejected on the ground of nonstatutory double patenting a s being unpatentable over claim s 1-7, respectively, of U.S. Patent No. 11,923,150 . Although the claims at issue are not identical, they are not patentably distinct from each other because claims 1-7 of U.S. Patent No. 11,923,150 recites all of the limitations in claims 1-7, respectively, of the instant application. Claim 8 is rejected on the ground of nonstatutory double patenting a s being unpatentable over claim 1 of U.S. Patent No. 11,923,150 . Although the claims at issue are not identical, they are not patentably distinct from each other because claim 1 of U.S. Patent No. 11,923,150 recites all of the limitations in claim 8 of the instant application. Claim 9 is rejected on the ground of nonstatutory double patenting a s being unpatentable over claim 8 of U.S. Patent No. 11,923,150 . Although the claims at issue are not identical, they are not patentably distinct from each other because claim 8 of U.S. Patent No. 11,923,150 recites all of the limitations in claim 9 of the instant application. Claim 10 is rejected on the ground of nonstatutory double patenting a s being unpatentable over claim 8 of U.S. Patent No. 11,923,150 . Although the claims at issue are not identical, they are not patentably distinct from each other because claim 8 of U.S. Patent No. 11,923,150 recites all of the limitations in claim 10 of the instant application. Claim 11 is rejected on the ground of nonstatutory double patenting a s being unpatentable over claim 9 of U.S. Patent No. 11,923,150 . Although the claims at issue are not identical, they are not patentably distinct from each other because claim 9 of U.S. Patent No. 11,923,150 recites all of the limitations in claim 11 of the instant application. Claim 12 is rejected on the ground of nonstatutory double patenting a s being unpatentable over claim 10 of U.S. Patent No. 11,923,150 . Although the claims at issue are not identical, they are not patentably distinct from each other because claim 10 of U.S. Patent No. 11,923,150 recites all of the limitations in claim 1 2 of the instant application. Claim 13 is rejected on the ground of nonstatutory double patenting a s being unpatentable over claim 11 of U.S. Patent No. 11,923,150 . Although the claims at issue are not identical, they are not patentably distinct from each other because claim 11 of U.S. Patent No. 11,923,150 recites all of the limitations in claim 13 of the instant application. Claim 14 is rejected on the ground of nonstatutory double patenting a s being unpatentable over claim 12 of U.S. Patent No. 11,923,150 . Although the claims at issue are not identical, they are not patentably distinct from each other because claim 12 of U.S. Patent No. 11,923,150 recites all of the limitations in claim 14 of the instant application. Claim 15 is rejected on the ground of nonstatutory double patenting a s being unpatentable over claim 11 of U.S. Patent No. 11,923,150 . Although the claims at issue are not identical, they are not patentably distinct from each other because claim 11 of U.S. Patent No. 11,923,150 recites all of the limitations in claim 15 of the instant application. Claim 16 is rejected on the ground of nonstatutory double patenting a s being unpatentable over claim 13 of U.S. Patent No. 11,923,150 . Although the claims at issue are not identical, they are not patentably distinct from each other because claim 13 of U.S. Patent No. 11,923,150 recites all of the limitations in claim 16 of the instant application. Claim 17 is rejected on the ground of nonstatutory double patenting a s being unpatentable over claim 14 of U.S. Patent No. 11,923,150 . Although the claims at issue are not identical, they are not patentably distinct from each other because claim 14 of U.S. Patent No. 11,923,150 recites all of the limitations in claim 17 of the instant application. Claim 18 is rejected on the ground of nonstatutory double patenting a s being unpatentable over claim 15 of U.S. Patent No. 11,923,150 . Although the claims at issue are not identical, they are not patentably distinct from each other because claim 15 of U.S. Patent No. 11,923,150 recites all of the limitations in claim 18 of the instant application. Claim 19 is rejected on the ground of nonstatutory double patenting a s being unpatentable over claim 16 of U.S. Patent No. 11,923,150 . Although the claims at issue are not identical, they are not patentably distinct from each other because claim 16 of U.S. Patent No. 11,923,150 recites all of the limitations in claim 19 of the instant application. Claim 20 is rejected on the ground of nonstatutory double patenting a s being unpatentable over claim 17 of U.S. Patent No. 11,923,150 . Although the claims at issue are not identical, they are not patentably distinct from each other because claim 17 of U.S. Patent No. 11,923,150 recites all of the limitations in claim 20 of the instant application. Claim Rejections - 35 USC § 103 In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis ( i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status. The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action: A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made. Claim(s) 1-12 are rejected under 35 U.S.C. 103 as being unpatentable over Park et al . (2015/0028450) in view of Gong et al. (2018/0158897). Re claim 1 , Park teaches a n integrated circuit (IC) structure (Fig. 3) , comprising: a substrate (20) having a first side (“bottom side”) and a second side (“top side”) ; a via (30) between the first side (“bottom side”) and the second side (“top side”) ; a capacitor (70Q) having a first electrode (72Q) , a second electrode (74Q) , and an insulator (76Q) between the first electrode (72Q) and the second electrode (74Q) ; and a dielectric material (40) on a sidewall of the via (30); wherein: the first electrode (72Q) includes a first conductive material on a sidewall and a bottom of an opening (80Q) in the substrate [66-68, 99] , the opening (80Q) extending from the second side (“top side”) towards the first side (“bottom side”) , the insulator (76Q) includes an insulator material over the sidewall and the bottom of the opening ([97-99], Fig. 3) , wherein the first conductive material is between the sidewall of the opening and the insulator material [66-68, 97-99] , the second electrode (74Q) includes a second conductive material filling [66-68, 97-99] at least a portion of the opening (80Q) with the first conductive material and the insulator material therein ([66-68, 97-99], Fig. 3). Park does not explicitly teach a dielectric material on a sidewall of the capacitor; and the dielectric material on the sidewall of the capacitor is between the first conductive material and the sidewall of the opening. Gong teaches a capacitor structure (Figs. 7a-d) comprising a dielectric material [43] on a sidewall of a capacitor (220) ; and the dielectric material [43] on the sidewall of the capacitor is between a conductive material (724) and a sidewall of an opening ([43], 734) . Therefore, it would have been obvious to one of ordinary skill in the art as of the effective filling date of the claimed invention to modify Park as taught by Gong in order to provide sufficient isolation for the first electrically conductive material ([43], Gong). Re claim 2 , Park in view of Gong teaches the IC structure according to claim 1 . Park in view of Gong does not explicitly teach wherein a depth of the opening is between about 1 and 25 micrometers. However, Applicant has not shown wherein a depth of the opening is between about 1 and 25 micrometers has a specific, disclosed criticality that is unexpected and would not have been determined through routine experimentation of one having ordinary skill in the art. Therefore, it would have been obvious to adjust the depth the opening so as to customize, optimize, or otherwise meet customer space and design requirements, since it has been held that where the general conditions of a claim are disclosed in the prior art, discovering the optimum or workable ranges involves only ro utine skill in the art. In re Al ler, 105 USPQ 233. Re claim 3 , Park in view of Gong teaches the IC structure according to claim 1, a depth of the opening is between about 1.1 and 4 times smaller than a distance between the first side and the second side (Fig. 3, Park) . Re claim 4 , Park in view of Gong teaches the IC structure according to claim 1 . Park in view of Gong does not explicitly teach wherein a width of the opening is between about 250 and 5000 nanometers. However, Applicant has not shown wherein a width of the opening is between about 250 and 5000 nanometers has a specific, disclosed criticality that is unexpected and would not have been determined through routine experimentation of one having ordinary skill in the art. Therefore, it would have been obvious to adjust the width the opening so as to customize, optimize, or otherwise meet customer space and design requirements, since it has been held that where the general conditions of a claim are disclosed in the prior art, discovering the optimum or workable ranges involves only ro utine skill in the art. In re Al ler, 105 USPQ 233. Re claim 5 , Park in view of Gong teaches the IC structure according to claim 1, wherein a thickness of the first conductive material is between about 10 and 70 nanometers ([72], element 72 is analogous to element 72Q, Park) . Re claim 6 , Park in view of Gong teaches the IC structure according to claim 1, wherein a thickness of the insulator material is between about 1 and 7 nanometers ([78], Park) . Re claim 7 , Park in view of Gong teaches the IC structure according to claim 1, further comprising: a first interconnect ([85, 99], Park) coupled to the first electrode (72Q, Park) , and a second interconnect (92, Park) coupled to the second electrode (74Q, Park) . Re claim 8 , Park in view of Gong teaches the IC structure according to claim 1, wherein the bottom of the opening is spaced apart from the first side (Fig. 3, Park) . Re claim 9 , Park in view of Gong teaches the IC structure according to claim 1, wherein a thickness of the dielectric material on the sidewall of the via (40, [77], Park) or a thickness of the dielectric material on the sidewall of the capacitor is between about 100 and 7000 nanometers (40, [77], Park) . Re claim 10 , Park in view of Gong teaches the IC structure according to claim 1, wherein a thickness of the dielectric material on the sidewall of the via is substantially equal to a thickness of the dielectric material on the sidewall of the capacitor (40, [77], Park, [43], Gong) . Re claim 11 , Park in view of Gong teaches the IC structure according to claim 1, wherein the dielectric material includes silicon and oxygen or nitrogen ([77], Park, [43], Gong) . Re claim 1 2 , Park in view of Gong teaches the IC structure according to claim 1, wherein the insulator material (76Q, Park) includes: one or more of hafnium, silicon, titanium, zirconium, tin, aluminum, and one or more of oxygen or nitrogen ([76, 99], Park) . Claim(s) 13-18 are rejected under 35 U.S.C. 103 as being unpatentable over Park et al . (2015/0028450) in view of Gong et al. (2018/0158897). Re claim 13 , Park teaches a n integrated circuit (IC) package (Figs. 1 & 7) , comprising: an IC die (320) having a first side (324) and a second side (326) ; and a further IC component (310) , coupled to the IC die (320) , wherein the IC die (320) further includes: a via (30) extending between the first side (324) and the second side (326) , an opening (80) extending from the second side towards, but not reaching, the first side (Fig. 1 ) , a layer of a first electrically conductive material (72) on sidewalls and a bottom of the opening (80) , a layer of an insulator material (74) on sidewalls and a bottom of the opening (80) with the layer of the first electrically conductive material (72) , a second electrically conductive material (76) in at least a portion of the opening (80) with the layer of the first electrically conductive material (72) and with the layer of the insulator material (74) , and a layer of a dielectric material (40) on sidewalls of the via (30) and on the sidewalls of the opening, wherein the layer of the dielectric material on the sidewalls of the opening is between the sidewalls of the opening and the layer of the first electrically conductive material. Park does not explicitly teach a dielectric material on the sidewalls of the opening, wherein the layer of the dielectric material on the sidewalls of the opening is between the sidewalls of the opening and the layer of the first electrically conductive material. Gong teaches a capacitor structure (Figs. 7a-d) comprising a dielectric material [43] on the sidewalls of an opening (734) , wherein the layer of the dielectric material (728) on the sidewalls of the opening is between the sidewalls of the opening and the layer of electrically conductive material (724) . Therefore, it would have been obvious to one of ordinary skill in the art as of the effective filling date of the claimed invention to modify Park as taught by Gong in order to provide sufficient isolation for the first electrically conductive material ([43], Gong). Re claim 14 , Park in view of Gong teaches the IC package according to claim 13, wherein a depth of the opening is between about 1.1 and 4 times smaller than a distance between the first side and the second side of the IC die (Figs. 1 & 7, Park) . Re claim 15 , Park in view of Gong teaches the IC package according to claim 13, wherein the via (30, Park) further includes a third electrically conductive material (32, Park) . Re claim 16 , Park in view of Gong teaches the IC package according to claim 13, wherein the further component is one of a package substrate, a flexible substrate, or an interposer ([119], Park) . Re claim 17 , Park in view of Gong teaches the IC package according to claim 13, wherein the further component is coupled to the IC die via one or more first level interconnects ([120-124], Park) . Re claim 18 , Park in view of Gong teaches the IC package according to claim 17, wherein the one or more first level interconnects include one or more solder bumps, solder posts, or bond wires ([120-124], Park) . Claim(s) 19-20 are rejected under 35 U.S.C. 103 as being unpatentable over Park et al . (2015/0028450) in view of Gong et al. (2018/0158897). Re claim 19 , Park teaches a method for fabricating an integrated circuit (IC) structure (Figs. 10A-O) , the method comprising: providing, in a support (402) , an opening (430) for a through-support via (TSV) (460) and a further opening (450) , wherein a depth of the further opening is between about 1.1 and 4 times smaller than a depth of the opening for the TSV (Fig. 10D) ; providing a first electrically conductive material (420) on sidewalls and a bottom of the further opening (450) ; providing an insulator material (446) on sidewalls and a bottom of the further opening (450) with the first electrically conductive material (420) ; providing a second electrically conductive material (452) in at least a portion of the further opening (450) with the first electrically conductive material (420) and with the insulator material (446) ; providing a third electrically conductive material (454) in a portion of the opening (430) for the TSV (460) ; and providing a layer of the dielectric material (440) on sidewalls of the opening (430) for the TSV (460) before providing the third electrically conductive material (454) in the portion of the opening (430) for the TSV (460) . Park does not explicitly teach providing a layer of a dielectric material on the sidewalls and the bottom of the further opening before providing the first electrically conductive material on the sidewalls and the bottom of the further opening . Gong teaches a capacitor structure (Figs. 7a-d) providing a layer of a dielectric material [43] on the sidewalls and the bottom of an opening (734) before providing an electrically conductive material (724) on the sidewalls and the bottom of the opening (734). Therefore, it would have been obvious to one of ordinary skill in the art as of the effective filling date of the claimed invention to modify Park as taught by Gong in order to provide sufficient isolation for the first electrically conductive material ([43], Gong). Re claim 20 , Park in view of Gong teaches the method according to claim 19, wherein the opening for the TSV extends from a front side of the support towards (Fig. 10B, Park) , but not reaching, a back side of the support (Fig. 10B, Park) , and the method further includes thinning the back side of the support to expose the third electrically conductive material (454, Park) from the back side (Figs. 10M-O, Park) . Conclusion Any inquiry concerning this communication or earlier communications from the examiner should be directed to FILLIN "Examiner name" \* MERGEFORMAT ADAM S BOWEN whose telephone number is FILLIN "Phone number" \* MERGEFORMAT (571)272-3984 . The examiner can normally be reached FILLIN "Work Schedule?" \* MERGEFORMAT M-F 9-5 . Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, FILLIN "SPE Name?" \* MERGEFORMAT Fernando Toledo can be reached at FILLIN "SPE Phone?" \* MERGEFORMAT 571-272-1867 . The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /FERNANDO L TOLEDO/ Supervisory Patent Examiner, Art Unit 2897 /ADAM S BOWEN/ Examiner, Art Unit 2897