DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 17-18 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
With regards to claim 17, the limitation of “the auxiliary gate region”… “forming an auxiliary gate region” without structurally defining the region is ambiguous.
Claim 17 recites the limitation "the auxiliary gate region" in line 12 pp 22. There is insufficient antecedent basis for this limitation in the claim.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 1-4, 16 & 17 is/are rejected under 35 U.S.C. 103 as being unpatentable over Hirler (US Pub no. 2017/0309713 A1) in view of Fang (CN 111370485 A)
Regarding claim 1, Hirler et al discloses A semiconductor power device comprising: a drift region(121) of a first conductivity type(n )[0032; a body region (115)of a second conductivity type(p) disposed over the drift region(121) fig. 5b[0041], wherein the second conductivity type is opposite to the first conductivity type fig. 5b;
at least two gate trench regions(165) in contact with the body region (115)and the
drift region(121)[0034][0072], and two laterally adjacent gate trench regions (165) are separated by a
mesa region (TS)fig. 5b; a contact region(110) of a first conductivity type(n+) located in the mesa region and disposed over the body region(115), wherein the contact region(110) has a higher doping concentration compared to a doping concentration of the drift region(121) fig. 5b, and wherein the contact region(110) is in contact with the two adjacent gate trench regions (165)so that, when in use, a channel is formed along each gate trench region(165) and in the body region(115)[0072]; a source contact (315)disposed over the contact region(110); an auxiliary gate region(155/150) formed in the mesa region(TS) and comprising at least one auxiliary trench gate(150);
wherein the at least two gate trench regions(165) are laterally spaced in a first
dimension, wherein current flows in the device in a second dimension
substantially transverse to the first dimension[0065], and wherein the gate trench
regions (165)extend in a third dimension of the device fig. 5b; Hirler et al fails to teach wherein the source contact is spaced from the auxiliary gate region in the third dimension.
However, Fang et al discloses wherein the source contact (109)is spaced from the gate region (106)in the third dimension(fig. 1)[0079][0085]. Since spacing the source contact from the gate region is one of finite solution to achieve sufficient channel concentration and decrease ON resistance, it would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to try in Hirler et al such that the source contact is spaced from the auxiliary gate region in the third dimension results since a person of ordinary skill has good reason to pursue the known options within his or her technical grasp. If this leads to the anticipated success, it is likely that product [was] not of innovation but of ordinary skill and common sense. KSR, 550 U.S. at 421, 82 USPQ2d at 1397
Regarding claim 2, Hirler et al discloses wherein the auxiliary gate region(150) extends from a surface of the contact region (110)to a first depth in the device, and wherein the first depth is substantially smaller than a total depth of the gate trench regions(165) in the device fig. 5b[0051].
Regarding claim 3, Hirler et al discloses wherein each gate trench region (160)comprises a gate conductive region (165)formed in an upper portion of each gate trench region(160), and a gate insulation layer(161) formed along sidewalls and a lower surface of each gate trench region(160) [0035].
Regarding claim 4, Hirler et al discloses wherein each gate trench region(1600) comprises a gate conductive region(165) formed in an upper portion of each gate trench region(160), and a gate insulation layer (161)formed along sidewalls and a lower surface of each gate trench region(160) [0035].
Regarding claim 16, Hirler et al discloses wherein the semiconductor device comprises a metal-oxide-semiconductor field-effect transistor (MOSFET)[0028].
Regarding claim 17, Hirler et al discloses A method of manufacturing a semiconductor power device, the method comprising the steps of: forming a drift region (121)of a first conductivity type(n-)[0032] fig. 5b; forming a body region(115) of a second conductivity type (p)over the drift region(121)[0041], wherein the second conductivity type is opposite to the first conductivity type fig. 5b; forming at least two gate trench regions(160) in contact with the body region(115) and the drift region(121) [0034] fig. 5b, and two laterally adjacent gate trench regions(160) separated by a mesa region(TS)[0040] fig. 5b, wherein the at least two gate trench regions (160)are laterally spaced in a first dimension fig. 5b, wherein current flows in the device in a second dimension substantially transverse to the first dimension fig. 5b, and wherein the gate trench regions(160) extend in a third dimension of the device(500) fig. 5b; forming a contact region (110)of a first conductivity type (n+)located in the mesa(TS)
region and disposed over the body region(115) fig. 5b, wherein the contact region(110) has a higher doping concentration compared to a doping concentration of the drift
region(121) fig. 5b, and wherein the contact region (110)is in contact with the two adjacent gate
trench(160) regions so that, when in use, a channel is formed along each gate trench(160) region and in the body region(115)[0071-0072]; forming a source contact(315) disposed over the contact region(110)[0057]; and forming an auxiliary gate region formed in the mesa region(TS), and at least one auxiliary trench gate(150).
;
Hirler et al fails to teach wherein the source contact is spaced from the auxiliary gate region in the third dimension.
However, Fang et al discloses wherein the source contact (109)is spaced from the gate region (106)in the third dimension(fig. 1)[0079][0085]. Since spacing the source contact from the gate region is one of finite solution to achieve sufficient channel concentration and decrease ON resistance, it would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to try in Hirler et al such that the source contact is spaced from the auxiliary gate region in the third dimension results since a person of ordinary skill has good reason to pursue the known options within his or her technical grasp. If this leads to the anticipated success, it is likely that product [was] not of innovation but of ordinary skill and common sense. KSR, 550 U.S. at 421, 82 USPQ2d at 1397
Claim(s) 5- 9 is/are rejected under 35 U.S.C. 103 as being unpatentable over Hirler (US Pub no. 2017/0309713 A1) in view of Fang (CN 111370485 A) as applied to claims 1& 3 and further in view of Schloesser (US Pub no. 2014/0084362 A1)
Regarding claim 5, Hirler et al as modified by Fang et al discloses all the claim limitations of claim 3 and further teaches wherein each gate trench region further
comprises a shield electrode in a lower portion of each gate trench region, wherein the
shield electrode is insulated from the drift region by the gate insulation layer but fails to teach wherein the shield electrode is insulated from the gate electrode by an insulation layer disposed over the shield electrode.
However, Schloesser et al discloses wherein the shield electrode (80) is insulated from the gate electrode(60) by an insulation layer(81) disposed over the shield electrode(80)[0031]. It would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to further modify HIrler et al & Fang et al with teachings of Schloesser et al to increase the number of channel regions per area.
Regarding claim 6, Schloesser et al discloses wherein the upper portion extends to a second depth in the device, wherein the second depth is substantially equal to the depth of the body region (30)in the device fig. 1a(upper portion designated by 60 is equal to the body 30).
Regarding claim 7, Schloesser et al discloses wherein the auxiliary gate region (150)extends from a surface of the contact region to a first depth in the device, and wherein the upper portion upper portion designated by 60 is equal to the body 30) extends to a second depth in the device, wherein the first depth is equal to or smaller than the second depth(fig. 1a).
Regarding claim 8, Schloesser et al discloses wherein the upper portion extends to a second depth in the device, wherein the second depth is substantially equal to the depth of the body region(30) in the device fig. 1a(upper portion designated by 60 is equal to the body 30).
Regarding claim 9 Hirler et al as modified by Fang et al discloses all the claim limitations of claim 1 but fails to teach wherein the auxiliary gate region has a width between two adjacent gate trench regions that is equal to or greater than 40% of a width of the mesa region.
Schloesser et al discloses all the claim limitations of claim 3 Schloesser et al discloses wherein the auxiliary gate region (150)has a width between two adjacent gate trench regions (65) but fails to teach that is equal to or greater than 40% of a width of the mesa region. It would have been obvious to one of ordinary skill in the art before the effective filing date to achieve equal to or greater than 40% of a width of the mesa region through routine experimentation to optimize current efficiency. "[W]here the general conditions of a claim are disclosed in the prior art, it is not inventive to discover the optimum or workable ranges by routine experimentation." In re Aller, 220 F.2d 454, 456, 105 USPQ 233, 235 (CCPA 1955)
Claim(s) 18 is/are rejected under 35 U.S.C. 103 as being unpatentable over Hirler (US Pub no. 2017/0309713 A1) in view of Fang (CN 111370485 A) as applied to claim 17 and further in view of Poelzl (US Pub no. 2016/0111504 A1).
Regarding claim 18, Hirler et al as modified by Fang et al discloses all the claim limitations of claim 17 but fails to teach wherein the step of forming an auxiliary gate region formed in the mesa region comprises: depositing a photoresist layer over a surface of the device; developing a mask in the photoresist layer, so that at least one area in the mesa region is exposed; and performing an etching process to form at least one recess defining the auxiliary gate region.
However, Poelzl et al discloses power MOSFET device wherein the step of forming an auxiliary gate region (152) formed in the mesa region comprises: depositing a photoresist layer(432) over a surface of the device[0030]; developing a mask in the photoresist layer(432), so that at least one area in the mesa region(170) is exposed[0040]; and performing an etching process to form at least one recess defining the auxiliary gate region(152) [0044][0030]. It would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to modify the invention of Hirler et and Fang et al with the teachings of Poelzl et al to perform a self-aligned process to avoid alignment tolerance.
Allowable Subject Matter
Claims 10-15 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
With regards to claim 10, the limitations including additional source contacts located at opposite sides of the gate trench regions was not found in prior art. Claims 11-13 are objected to since the claims depend from claim 10. Claims 14-15 are objected to since the claims depend from claim 13 and claim 14 respectively.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to LATANYA N CRAWFORD EASON whose telephone number is (571)270-3208. The examiner can normally be reached Monday-Friday 8:30 AM-4:30 PM.
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/LATANYA N CRAWFORD EASON/ Primary Examiner, Art Unit 2813
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