Prosecution Insights
Last updated: October 01, 2026
Application No. 18/397,008

ELECTROSTATIC DEVICE

Non-Final OA §102§103
Filed
Dec 27, 2023
Examiner
CRAWFORD EASON, LATANYA N
Art Unit
2813
Tech Center
2800 — Semiconductors & Electrical Systems
Assignee
Globalfoundries Singapore Pte. Ltd.
OA Round
1 (Non-Final)
78%
Grant Probability
Favorable
1-2
OA Rounds
0m
Est. Remaining
79%
With Interview

Examiner Intelligence

Grants 78% — above average
78%
Career Allowance Rate
731 granted / 932 resolved
+10.4% vs TC avg
Minimal +0% lift
Without
With
+0.4%
Interview Lift
resolved cases with interview
Typical timeline
2y 8m
Avg Prosecution
41 currently pending
Career history
977
Total Applications
across all art units

Statute-Specific Performance

§101
0.4%
-39.6% vs TC avg
§103
54.7%
+14.7% vs TC avg
§102
30.7%
-9.3% vs TC avg
§112
11.2%
-28.8% vs TC avg
Black line = Tech Center average estimate • Based on career data from 932 resolved cases

Office Action

§102 §103
DETAILED ACTION Notice of Pre-AIA or AIA Status The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . Election/Restrictions The restriction requirement mailed on 6/03/2026 has been withdrawn. Currently claims 1-20 are pending. Claim Rejections - 35 USC § 102 The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action: A person shall be entitled to a patent unless – (a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention. Claim(s) 1-6, & 20 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Kitch (US Patent 6,495,904 B1). Regarding claim 1, Kitch et al discloses A structure comprises: a device comprising a collector region(206), an emitter region(232), and a base region(210) (col. 6, lines 10-12 & col. 7, lines 55-57); an oxidation structure(214 or 216) within the base region(210) (col. 6, lines 49-50); and an isolation structure(212 or 212 & 214) abutting the oxidation structure (214 or 216)and extending between the base region(210) and the emitter region(232) (col. 6, lines 40-45) fig. 11 (Examiner notes that the isolation structure (212 or 212 & 214)is disposed within a side surface of the base region (210) such that portions of the isolation structure extend between a bottom surface of the emitter region (232)and a bottom surface of the base region(210)). Regarding claim 2, Kitch et al discloses wherein the oxidation structure(214) comprises a local oxidation (LOCOS) in a semiconductor substrate(200) (col. 5, line 65) in the base region(210)(col. 6 lines 40-45 and lines 51-56). Regarding claim 3, Kitch et al discloses wherein the oxidation structure(214 or 216) is a raised isolation structure above a surface of the semiconductor substate(200) and extending below the surface of the semiconductor substrate(200) fig. 11. Regarding claim 4, Kitch et al discloses further comprising polysilicon material(218/226) on the oxidation structure(214 or 216)(col. 6, lines 58-60) fig. 11. Regarding claim 5, Kitch et al discloses wherein the polysilicon material (226) electrically connects to a diffusion region(230) in the collector region(206) fig. 11. Regarding claim 6, Kitch et al discloses wherein the oxidation structure (216)extends between a diffusion region (208)in the collector region(206) and contacts the isolation structure(214)( fig. 11). Regarding claim 20, Kitch et al discloses a method comprises: forming a device comprising a collector region(206), an emitter region(232), and a base region(210) (col. 6, lines 10-12 & col. 7, lines 55-57);forming an oxidation structure (214)within the base region(210) (col. 6, lines 49-50); and forming an isolation structure (212)abutting the oxidation structure(214) and extending between the base region (210) and the emitter region(232) (col. 6, lines 40-44) fig. 11 (Examiner notes that the isolation structure (212)is disposed within a side surface of the base region (210) such that portions of the isolation structure extend between a bottom surface of the emitter region (232)and a bottom surface of the base region(210)). Claim(s) 1, 6 & 20 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Zhan US Pub 2014/0061716 A1). Regarding claim 1, Zhan et al discloses A structure comprises: a device comprising a collector region(114), an emitter region(122), and a base region(121 or 118)[0035]; an oxidation structure(120) within the base region(121 or 118)[0034-0035]; and an isolation structure (123)[0032]abutting the oxidation structure (120)and extending between the base region (121 or 118)and the emitter region(122) (extends the upper surface of base and emitter) fig. 2. Regarding claim 6, Zhan et al discloses wherein the oxidation structure (120)extends between a diffusion region (NSD)in the collector region(128) and contacts the isolation structure(123) fig. 2. Regarding claim 20, Zhan et al discloses a method comprises: forming a device comprising a collector region(114), an emitter region(122), and a base region(121 or 118) [0035]; forming an oxidation structure(120) within the base region(121 or 118)[0034-0035; and forming an isolation structure (123)[0032]abutting the oxidation structure (120)and extending between the base region(121 or 118) and the emitter region(122) fig. 2. Claim Rejections - 35 USC § 103 The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action: A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made. Claim(s) 2 , 3, 9, & 10 is/are rejected under 35 U.S.C. 103 as being unpatentable over Zhan US Pub 2014/0061716 A1) in view of Kitch (US Patent 6,495,904 B1). Regarding claim 2, Zhan et al discloses all the claim limitations of claim 1 and further teaches wherein the oxidation structure (123)comprises STI regions can be used to replace silicide block patterns(123) in a semiconductor substrate (102)in the base region(118) fig. 2[0032] but fails to teach local oxidation (LOCOS). However, Kitch et al discloses using LOCOS technique to provide isolation regions (col. 6 , lines 51-55). It would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to modify Zhan et al with the teachings of Kitch et al since the claim would have been obvious because a particular known technique was recognized as part of the ordinary capabilities of one skilled in the art. One of ordinary skill in the art would have been capable of applying LOCOS process to a known device (method, or product) that was ready for improvement, and the results would have been predictable to one of ordinary skill in the art. In re Nilssen, 851 F.2d 1401, 7 USPQ2d 1500 (Fed. Cir. 1988) Regarding claim 3 , Kitch et al discloses wherein the oxidation structure(214 or 216) is a raised isolation structure above a surface of the semiconductor substate(200) and extending below the surface of the semiconductor substrate(200) fig. 11. Regarding claim 9, Zhan et al discloses wherein the isolation structure comprises a shallow trench isolation structure (123 (STI [0032])extending within a first well (112)of a first conductivity type (P or N) [0026]and is adjacent to a diffusion region (116)of a second conductivity type within the first well(112) fig. 2[0030] Regarding claim 10, Zhan et al discloses wherein the first conductivity type comprises an n-type dopant [0026]and the second conductivity type[0030] but fails to teach p-type. However, Zhan et al teaches the doping regions can be interchangeable depending on the resulting device [0013]. It would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to modify the second conductivity type to a p-type since interchanging doped region was held to be an obvious matter of design choice In re Japikse, 181 F.2d 1019, 86 USPQ 70 (CCPA 1950). Claim(s) 7 & 8 is/are rejected under 35 U.S.C. 103 as being unpatentable over Zhan US Pub 2014/0061716 A1). Regarding claim 7, Zhan et al discloses all the claim limitations of claim 6 and further teaches herein the diffusion region comprises an n-type dopant(NSD) within a N-well (114)and a N-drift region(116) [0027][0030]but fails to teach wherein the diffusion region comprises a p-type dopant within a P-well and a P-drift region. However, Zhan et al teaches the doping regions can be interchangeable depending on the resulting device [0013]. It would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to achieve the diffusion region comprises a p-type dopant within a P-well and a P-drift region since interchanging doped region to obtain a particular device was held to be an obvious matter of design choice In re Japikse, 181 F.2d 1019, 86 USPQ 70 (CCPA 1950). Regarding claim 8, Zhan et al discloses further comprising a P+ buried isolation layer(108) in a semiconductor substrate(102) [0023], wherein the P-drift region(116) and the P+ buried isolation layer(108) isolate an N+ drift region of the base region(118-doping regions are interchangeable ) fig. 2. Claim(s) 13 is/are rejected under 35 U.S.C. 103 as being unpatentable over Zhan US Pub 2014/0061716 A1) in view of Shih (11031303 B1). Regarding claim 13, Zhan et al discloses further comprising a deep trench isolation structure comprising insulator material (106), the second deep trench isolation structure (106)isolating the emitter region(122), the collector region(128) and the base region(121) [0029][0035] fig. 2but fails to teach a deep trench isolation structure comprising an insulator lining material and filled polysilicon material. However, Shih et al discloses deep trench isolation structures (106) comprising an insulator lining material (110)and filled polysilicon material(113)(col. 3, lines 39-41; col. 7, lines 45-50). It would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to modify Zhan et al with the teachings of Shih et al to electrically isolate high voltage devices from low voltage devices and/or regions. Claim(s) 14 is/are rejected under 35 U.S.C. 103 as being unpatentable over Zhan US Pub 2014/0061716 A1) in view of Shih (11031303 B1) as applied to claim 13 and further in view of Salman (US Pub no. 2020/0328204 A1). Regarding claim 14, Zhan et al as modified by Shih et al discloses all the claim limitations of claim 13 but fails to teach wherein the polysilicon material comprises P-doped polysilicon and extends to an underlying semiconductor substrate beneath an N+ buried layer. However, Salman et al discloses a polysilicon material (122)comprises P-doped polysilicon and extends to an underlying semiconductor substrate (102)beneath an N+ buried layer(106)[0017]. It would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to further modify Zhan et al & Shih et al with the teachings of Salman et al to form a boundary between the circuit components and bipolar transistor. Claim(s) 15 is/are rejected under 35 U.S.C. 103 as being unpatentable over Zhan (US Pub no. 2014/0347771 A1) in view of Zhan US Pub 2014/0061716 A1) Regarding claim 15, Zhan et al (‘771) discloses a structure comprising: a collector region(352) comprising a N-drift region(338) in a semiconductor substrate(302)[0042][0035]; an emitter region(354) comprising a diffusion region(354) in a well (344) and silicide blocking regions (360) including oxide materials adjacent to the diffusion region(354)[0042-0043]; a base region(344/348) within a drift region(312) in the semiconductor substrate(302)[0045]; and a local oxidation(334/332) in the base region(344/348), extending from the N-drift region (338)and contacting the silicide blocking regions (360) (fig. 13). Zhan et al (‘771) fails to teach a p-type drift, p+ diffusion in a N-well and a shallow isolation structure adjacent to the p+ diffusion region; base region within an N-drift region; the local oxidation extending from the P-drift region and contacting the shallow trench isolation structure. However, Zhan et al (‘771) discloses that the subject matter is not intended to be limiting and further teaches that the conductivity of the doped regions can be interchanged[0023]. Therefore it would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to modify the NPN bipolar junction transistor elements taught by Zhan et al(‘771) with a collector comprising a p-type drift; an emitter region having a p+ diffusion in a N-well; a base region within an N-drift region to implement a device in an equivalent manner for PNP bipolar junction transistor since interchanging doped region was held to be an obvious matter of design choice In re Japikse, 181 F.2d 1019, 86 USPQ 70 (CCPA 1950). In a similar endeavor, Zhan et al (‘716) discloses silicon blocking regions 123 can be replaced using STI [0032]. It would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to modify Zhan et al (‘771)with the teachings of Zhan et al (‘716) such that the local oxidation extending from the P-drift region and contacting the shallow trench isolation structure results since the claim would have been obvious because the substitution of one known element for another yields predictable results to one of ordinary skill in the art. In re Fout, 675 F.2d 297, 213 USPQ 532 (CCPA 1982) Claim(s) 16 is/are rejected under 35 U.S.C. 103 as being unpatentable over in Zhan (US Pub no. 2014/0347771 A1) in view of Zhan US Pub 2014/0061716 A1) as applied to claim 15, and further in view of Salman (US Pub no. 2019/0181134 A1). Regarding claim 16, Zhan et al (‘771) as modified by Zhan et al (‘716) discloses all the claim limitations of claim 15 but fails to teach wherein the local oxidation in the base region is raised above a top surface of the semiconductor substrate and extends below the top surface of the semiconductor substrate. However, Salman et al discloses isolation structures 126 (STI or FOX)are formed in and above select portions of the upper surface of the third epitaxial layer 112[0017]. It would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to further modify Zhan et al (‘771) & Zhan et al (‘716) with the teachings of Salman et al to provide electrical isolation between various structures. Allowable Subject Matter Claims 11, 12, 17-19 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims. The cited reference, Zeng US Patent 12, 727,254 B2 & Song 11,908.895 B2 is noted as general background of the art. Conclusion Any inquiry concerning this communication or earlier communications from the examiner should be directed to LATANYA N CRAWFORD EASON whose telephone number is (571)270-3208. The examiner can normally be reached Monday-Friday 8:30 AM-4:30 PM. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Steven B Gauthier can be reached at (571)270-0373. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /LATANYA N CRAWFORD EASON/Primary Examiner, Art Unit 2813
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Prosecution Timeline

Dec 27, 2023
Application Filed
Sep 10, 2026
Non-Final Rejection mailed — §102, §103 (current)

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Prosecution Projections

1-2
Expected OA Rounds
78%
Grant Probability
79%
With Interview (+0.4%)
2y 8m (~0m remaining)
Median Time to Grant
Low
PTA Risk
Based on 932 resolved cases by this examiner. Grant probability derived from career allowance rate.

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