Prosecution Insights
Last updated: May 29, 2026
Application No. 18/397,252

SEMICONDUCTOR DEVICE

Non-Final OA §102
Filed
Dec 27, 2023
Priority
Jan 13, 2023 — JP 2023-004022
Examiner
YI, CHANGHYUN
Art Unit
2812
Tech Center
2800 — Semiconductors & Electrical Systems
Assignee
Sumitomo Electric Industries, Ltd.
OA Round
1 (Non-Final)
94%
Grant Probability
Favorable
1-2
OA Rounds
0m
Est. Remaining
98%
With Interview

Examiner Intelligence

Grants 94% — above average
94%
Career Allowance Rate
1001 granted / 1067 resolved
+25.8% vs TC avg
Minimal +4% lift
Without
With
+4.2%
Interview Lift
resolved cases with interview
Fast prosecutor
1y 9m
Avg Prosecution
41 currently pending
Career history
1112
Total Applications
across all art units

Statute-Specific Performance

§101
2.4%
-37.6% vs TC avg
§103
61.1%
+21.1% vs TC avg
§102
18.4%
-21.6% vs TC avg
§112
8.4%
-31.6% vs TC avg
Black line = Tech Center average estimate • Based on career data from 1067 resolved cases

Office Action

§102
Notice of Pre-AIA or AIA Status The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . DETAILED ACTION Title The title of the invention is not descriptive. A new title is required that is clearly indicative of the invention to which the claims are directed. (see MPEP § 606.01). This may result in slightly longer titles, but the loss in brevity of title will be more than offset by the gain in its informative value in indexing, classifying, searching, etc. The following title is suggested: “III-N High Electron Mobility Transistor (HEMT) with Large Bandgap Back Barrier Layer” Claim Rejections - 35 USC § 102 The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action: A person shall be entitled to a patent unless – (a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale or otherwise available to the public before the effective filing date of the claimed invention. (a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention. Claims 1-6 are rejected under 35 U.S.C. 102 (a)(1) and (a)(2) as being anticipated by Chen (US 20220029007). Regarding claim 1. Fig 1 of Chen discloses A semiconductor device 500, comprising: a substrate 102 [0018]; a buffer layer 108 above the substrate ([0031]: ‘improving the epitaxial quality of the resistive layer and reducing the epitaxial defeats so as to inhibit the leakage current’. Thus, being a buffer layer); a barrier layer 112 on the buffer layer [0031]; an electron traveling layer 114 ([0035]: channel layer) on the barrier layer; and an electron supply layer 116 (the wide bandgap AlN creates strong polarization-induced charges at the AlN/GaN interface. Thus, polarization effect supplies electrons to adjacent GaN electron traveling layer (channel) 114. Thus, 116 is an electron supply layer) above the electron traveling layer, wherein the electron traveling layer ([0063]: 200 – 500 nm) is thinner than the buffer layer ([0032]: 0.5-5 μm), and a band gap of the barrier layer ([0056]: AlN) is larger than a band gap of the buffer layer ([0031]: GaN) and a band gap of the electron traveling layer ([0057]: GaN) ([0059: the bandgap of AlN is 6.2 eV whereas the bandgap of GaN is 3.4 eV). Regarding claim 2. Chen discloses The semiconductor device according to claim 1, wherein both of the buffer layer and the electron traveling layer are a GaN layer [0031]/[0057], and the barrier layer is an AlxInyGa1-x-yN layer (0 < x ≤ 1, 0 ≤ y ≤ 0.1) ([0056]: 112 is AlN, which means Al1In0Ga1-1-0N = AlN, thus Chen discloses the claimed composition range). Regarding claim 3. Chen discloses The semiconductor device according to claim 2, wherein a relation of “y + 0.8 ≤ x” is established (Chen discloses y = 0, x = 1. Thus, 0 + 0.8 ≤ 1). Regarding claim 4. Chen discloses The semiconductor device according to claim 1, wherein a thickness of the barrier layer is 2 nm or larger and 20 nm or smaller ([0063]: 5 nm). Regarding claim 5. Chen discloses The semiconductor device according to claim 1, wherein a thickness of the buffer layer is 20 μm or smaller ([0032]: 0.5-5 μm). Regarding claim 6. Chen discloses The semiconductor device according to claim 1, wherein a thickness of the electron traveling layer is 200 nm or larger ([0063]: 200 – 500 nm). Conclusion Any inquiry concerning this communication or earlier communications from the examiner should be directed to Changhyun Yi whose telephone number is (571)270-7799. The examiner can normally be reached Monday-Friday: 8A-4P. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Davienne Monbleau can be reached on 571-272-1945. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /Changhyun Yi/Primary Examiner, Art Unit 2812
Read full office action

Prosecution Timeline

Dec 27, 2023
Application Filed
Mar 09, 2026
Non-Final Rejection mailed — §102 (current)

Precedent Cases

Applications granted by this same examiner with similar technology

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SEMICONDUCTOR STRUCTURE AND METHOD FOR FORMING THE SAME
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Patent 12641830
VERTICAL SELF ALIGNED GATE ALL AROUND TRANSISTOR
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Patent 12641863
SEMICONDUCTOR STRUCTURE AND METHOD FOR FORMING THE SAME
3y 0m to grant Granted May 26, 2026
Patent 12641831
GATE STRUCTURES OF SEMICONDUCTOR DEVICES AND FABRICATION METHODS THEREOF
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Patent 12635164
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3y 0m to grant Granted May 19, 2026
Study what changed to get past this examiner. Based on 5 most recent grants.

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Prosecution Projections

1-2
Expected OA Rounds
94%
Grant Probability
98%
With Interview (+4.2%)
1y 9m (~0m remaining)
Median Time to Grant
Low
PTA Risk
Based on 1067 resolved cases by this examiner. Grant probability derived from career allowance rate.

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