DETAILED ACTION
Election/Restrictions
Regarding the applicant’s arguments/remarks in the response received on 04/10/2026, Examiner finds applicant’s arguments persuasive. Therefore, the Requirement for Restriction is withdrawn. Claims 1-19 are currently pending in the application.
Priority
Receipt is acknowledged of certified copies of papers required by 37 CFR 1.55.
Information Disclosure Statement
The information disclosure statement (IDS) submitted on 12/27/2023 is in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statement is being considered by the examiner.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1-4, 7-14, 16, and 19 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by O’BRIEN et al. (US 20240222482 A1), hereinafter “O’Brien.”
Re: Claim 1. O’Brien discloses a semiconductor device (Fig. 1: transistor structure 100; ¶0021: GAA transistor, dual gate transistor, or nanoribbon transistor) comprising:
a channel layer comprising a two-dimensional (2D) semiconductor material (Fig. 1: metal chalcogen layers 110), a channel portion (Fig. 1: channel region 143), and an extension portion on both sides of the channel portion (Fig. 1: S/D contact regions 141 and spacer region 142; ¶0022: metal chalcogen layers 110 also include source and drain contact regions 141 and a spacer region 142 that are outside of channel region 143);
a source electrode and a drain electrode on both sides of the channel layer (Fig. 1: source structure 130 and drain structure 132), respectively;
a gate electrode surrounding the channel portion (Fig. 1: gate electrode 108 and gate structure 109; ¶0021: GAA transistor);
a first insulating layer between the channel portion of the channel layer and the gate electrode (Fig. 1: gate dielectric 112; ¶0064: Gate dielectric 112 may have a high relative permittivity (i.e., dielectric constant, K). In some high-K gate dielectric embodiments, gate dielectric 112 is a metal oxide including oxygen and one or more metals, such as, but not limited to, aluminum, hafnium, zirconium, tantalum, or titanium. In some embodiments, gate dielectric 112 is silicon oxide.); and
a second insulating layer on the extension portion of the channel layer (Fig. 1: spacer region 142 is outside of channel region 143 which comprises spacer 113), a material of the second insulating layer being different than a material of the first insulating layer (¶0033: Spacer 113 may include any suitable insulative material or materials such as low k dielectric material.),
wherein the second insulating layer comprises at least one of an n-type dopant or a p-type dopant (Fig. 1: doping layer 111 and spacers 113 surround extensions in the stacked nanoribbon structure; ¶0033: Spacer 113 may include any suitable insulative material or materials such as low k dielectric material. As shown, spacer 113 is directly on doping layers 111 in spacer region 142 of metal chalcogen layers 110. By providing doping layers 111, i.e., dopants may be n- or p- type in spacer region 142 of metal chalcogen layers 110, transistor structure 100 has improved conductivity in spacer region 142.), and
a dopant in the extension portion is the same as a dopant in the second insulating layer (Fig. 1: doping layer 111 and spacers 113 surround extensions in the stacked nanoribbon structure; ¶0026 discloses that doping layers 111 may also be characterized as material layers and lists various examples of dopants that may be used; ¶0027: when metal chalcogen layers 110 are p-type, doping layers 111 provide p-type doping and when metal chalcogen layers 110 are n-type, doping layers 111 provide n-type doping; ¶0028 discloses various examples of n-type dopants which may be used; Also see ¶0035 and ¶0037; In other words, n- or p- type tuning can be achieved depending on TMD and metal chosen.).
Re: Claim 2, O’Brien discloses the semiconductor device of claim 1, and
wherein the first insulating layer surrounds the channel portion (Fig. 1: gate dielectric 112 surrounds channel region/portion 143), and
the second insulating layer surrounds the extension portion (Fig. 1: doping layer 111 and spacers 113 surround extensions in the stacked nanoribbon structure).
Re: Claim 3, O’Brien discloses the semiconductor device of claim 1, and
wherein the second insulating layer comprises at least one of an aluminum oxide, a hafnium oxide, a zirconium oxide, or a combination thereof (¶0026: doping layers 111 may include oxygen and a metal… one or more of doping layers 111 may be one of germanium oxide, aluminum oxide).
Re: Claim 4, O’Brien discloses the semiconductor device of claim 1, and
wherein the second insulating layer comprises an insulating material having a dielectric constant less than a dielectric constant of the first insulating layer (¶0033: Spacer 113 may include any suitable insulative material or materials such as low k dielectric material, distinct from high-k gate dielectric 112; ¶0064: Gate dielectric 112 may have a high relative permittivity (i.e., dielectric constant, K). In some high-K gate dielectric).
Re: Claim 7, O’Brien discloses the semiconductor device of claim 1, and
wherein the channel layer comprises two or more channel layers (Fig. 1: multiple channel layers 110).
Re: Claim 8, O’Brien discloses the semiconductor device of claim 1, and
further comprising: at least one supporting layer on the channel layer (¶0022: As shown in enlarged view 150, metal chalcogen layers 110 also include source and drain contact regions 141 and a spacer region 142 that are outside of channel region 143. Source and drain contact regions 141 are immediately adjacent source structure 130 and drain structure 132 such that, absent doping layers 111, source structure 130 and drain structure 132 would otherwise contact metal chalcogen layers 110. Similarly, spacer region 142 is immediately adjacent spacer 113 such that, absent doping layers 111, i.e., support layer, spacer 113 would otherwise contact metal chalcogen layers 110.).
Re: Claim 9, O’Brien discloses the semiconductor device of claim 8, and
wherein the supporting layer comprises at least one of a hafnium oxide or an aluminum oxide (¶0026: Doping layers 111 may also be characterized as material layers and, in some embodiments, one or more of doping layers 111 is a metal oxide… aluminum oxide).
Re: Claim 10, O’Brien discloses the semiconductor device of claim 1, and
wherein the 2D semiconductor material comprises an n-type semiconductor material or a p-type 2D semiconductor material (See ¶¶ 0027-0028: TMD’s explicitly classified as n-type or p-type with corresponding doping-layer choices).
Re: Claim 11, O’Brien discloses the semiconductor device of claim 10, and
wherein the n-type 2D semiconductor material comprises at least one of MoS2, MoSe2, MoTe2, or WS2 (¶0024: one or more of metal chalcogen layers 110 are stoichiometric TMDs. For example, one or more of metal chalcogen layers 110 may be MoS2, WS2, MoSe2, WSe2, MoTe2, or WTe2.).
Re: Claim 12, O’Brien discloses the semiconductor device of claim 10, and
wherein the p-type 2D semiconductor material comprises at least one of WSe2, MoTe2, or PtSe2 (¶0028: In some embodiments, metal chalcogen layers 110 are p-type such as MoS2, or WS2).
Re: Claim 13, O’Brien discloses the semiconductor device of claim 1, and
wherein the 2D semiconductor material comprises transition metal dichalcogenide (TMD) (¶0024: one or more of metal chalcogen layers 110 are stoichiometric TMDs.).
Re: Claim 14, O’Brien discloses the semiconductor device of claim 13, and
wherein the TMD comprises one of molybdenum (Mo), tungsten (W), niobium (Nb), vanadium (V), tantalum (Ta), titanium (Ti), zirconium (Zr), hafnium (Hf), technetium (Tc), and rhenium (Re), and a chalcogen element selected from sulfur (S), selenium (Se), and tellurium (Te) (¶0028: For example, the transition metal of metal chalcogen layers 110 may be molybdenum or tungsten, the chalcogen of metal chalcogen layers 110 maybe sulfur, and the metal of doping layers 111 may be one of lanthanum, magnesium, scandium, yttrium, or gadolinium.).
Re: Claim 16, O’Brien discloses a semiconductor device comprising (Fig. 1: transistor structure 100; ¶0021: GAA transistor, dual gate transistor, or nanoribbon transistor):
a channel layer comprising a two-dimensional (2D) semiconductor material (Fig. 1: metal chalcogen layers 110), a channel portion (Fig. 1: channel region 143), and an extension portion on both sides of the channel portion (Fig. 1: S/D contact regions 141 and spacer region 142; ¶0022: metal chalcogen layers 110 also include source and drain contact regions 141 and a spacer region 142 that are outside of channel region 143);
a source electrode and a drain electrode on both sides of the channel layer (Fig. 1: source structure 130 and drain structure 132), respectively;
a gate electrode on the channel portion (Fig. 1: gate electrode 108 and gate structure 109; ¶0021: GAA transistor);
a first insulating layer between the channel portion of the channel layer and the gate electrode (Fig. 1: gate dielectric 112; ¶0064: Gate dielectric 112 may have a high relative permittivity (i.e., dielectric constant, K). In some high-K gate dielectric embodiments, gate dielectric 112 is a metal oxide including oxygen and one or more metals, such as, but not limited to, aluminum, hafnium, zirconium, tantalum, or titanium. In some embodiments, gate dielectric 112 is silicon oxide.); and
a second insulating layer on the extension portion of the channel layer (Fig. 1: spacer region 142 is outside of channel region 143 which comprises spacer 113),
wherein a material of the second insulating layer is different from a material of the first insulating layer (¶0033: Spacer 113 may include any suitable insulative material or materials such as low k dielectric material.).
Re: Claim 19, O’Brien discloses an electronic device comprising (Fig. 6: stand-alone packaged device within data server machine 606):
the semiconductor device according to claim 16 (Fig. 6: processor circuitry 640).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 5 and 6 are rejected under 35 U.S.C. 103 as being unpatentable over O’BRIEN et al. (US 20240222482 A1).
Re: Claim 5, O’Brien discloses the semiconductor device of claim 1.
O’Brien discloses a metal-oxide doping layer (second insulating layer) formed selectively on TMD extensions outside the channel region (see ¶0018 and ¶0035). This layer induces charge transfer doping by creating a tunable interface (see ¶0018 and ¶0020). Specifically, “the non-stoichiometric metal oxide may be considered a material with a band structure such that the electron affinity of the material varies or is tuned based on its stoichiometry, which changes the density of charge carriers at the interface with the TMD material and, therefore, contact resistance (¶0018).
O’Brien differs from claim 5 in that it does not expressly disclose wherein the second insulating layer comprises an insulating material having a band offset of about 200 meV or less with the 2D semiconductor material. However, O’Brien teaches the general conditions of adjusting metal choice and stoichiometry to achieve the desired doping level, Vt shift, and low contact resistance that affect band offset/alignment.
Band-offset/alignment at this interface is thus a result-effective variable that a person of ordinary skill in the art would routinely optimize by adjusting metal choice and stoichiometry to achieve the desired doping level, Vt shift, and low contact resistance (See ¶0018, ¶0026, and ¶0027).
Therefore, a person having ordinary skill in the art before the effective filing date, motivated by the objective to improve the density of charge carriers at the interface with the TMD material and contact resistance would have routinely experimented with known fabrication variables disclosed by O’Brien in order to determine optimal values. Such routine optimization within the general conditions taught by O’Brien would have naturally led to a band offset of about 200 meV or less, as demonstrated by predictable enhancements in the density of charge carriers at the interface and improved contact resistance (reasonable expectation of success given O’Brien’s teachings on parameter effects). See MPEP § 2144.05(II)(“[W]here the general conditions of a claim are disclosed in the prior art, it is not inventive to discover the optimum or workable ranges by routine experimentation” (citing In re Aller, 220 F.2d 454, 456, 105 USPQ 233, 235 (CCPA 1955)).
Re: Claim 6, O’Brien discloses the semiconductor device of claim 1.
O’Brien discloses a metal-oxide doping layer (second insulating layer) formed selectively on TMD extensions outside the channel region (see ¶0018 and ¶0035). This layer induces charge transfer doping by creating a tunable interface (see ¶0018 and ¶0020). Specifically, “the non-stoichiometric metal oxide may be considered a material with a band structure such that the electron affinity of the material varies or is tuned based on its stoichiometry, which changes the density of charge carriers at the interface with the TMD material and, therefore, contact resistance (¶0018).
O’Brien differs from claim 6 in that it does not expressly disclose wherein the second insulating layer comprises an insulating material having a band offset of about 50 meV or greater with the 2D semiconductor material. However, O’Brien teaches the general conditions of adjusting metal choice and stoichiometry to achieve the desired doping level, Vt shift, and low contact resistance that affect band offset/alignment.
Band-offset/alignment at this interface is thus a result-effective variable that a person of ordinary skill in the art would routinely optimize by adjusting metal choice and stoichiometry to achieve the desired doping level, Vt shift, and low contact resistance (See ¶0018, ¶0026, and ¶0027).
Therefore, a person having ordinary skill in the art before the effective filing date, motivated by the objective to improve the density of charge carriers at the interface with the TMD material and contact resistance would have routinely experimented with known fabrication variables disclosed by O’Brien in order to determine optimal values. Such routine optimization within the general conditions taught by O’Brien would have naturally led to a band offset of about 50 meV or greater, as demonstrated by predictable enhancements in the density of charge carriers at the interface and improved contact resistance (reasonable expectation of success given O’Brien’s teachings on parameter effects). See MPEP § 2144.05(II)(“[W]here the general conditions of a claim are disclosed in the prior art, it is not inventive to discover the optimum or workable ranges by routine experimentation” (citing In re Aller, 220 F.2d 454, 456, 105 USPQ 233, 235 (CCPA 1955)).
Claim 15 is rejected under 35 U.S.C. 103 as being unpatentable over O’BRIEN et al. (US 20240222482 A1) in view of CHOU et al. (US 20230008409 A1), hereinafter “Chou.”
Re: Claim 15, O’Brien discloses semiconductor device of claim 1.
While O’Brien lists various examples of 2D semiconductor materials, it does not specifically disclose wherein the 2D semiconductor material comprises black phosphorus.
In a similar field of endeavor, Chou discloses wherein the 2D semiconductor material comprises black phosphorus (¶0026: The 2D semiconductor materials are promising candidates of the channel, source, drain materials of transistors. Examples of 2D semiconductor materials include transition metal dichalcogenides (TMDs), … black phosphorus or the like.).
Therefore, it would have been obvious to a person having ordinary skill in the art before the effective filing date, to have modified a material in the semiconductor disclosed by O’Brien with the material black phosphorus as disclosed in Chou in order to achieve a high electron mobility value (See Chou, ¶0026).
Claims 17 and 18 are rejected under 35 U.S.C. 103 as being unpatentable over O’BRIEN et al. (US 20240222482 A1).
Re: Claim 17, O’Brien discloses semiconductor device of claim 16.
O’Brien discloses a metal-oxide doping layer (second insulating layer) formed selectively on TMD extensions outside the channel region (see ¶0018 and ¶0035). This layer induces charge transfer doping by creating a tunable interface (see ¶0018 and ¶0020). Specifically, “the non-stoichiometric metal oxide may be considered a material with a band structure such that the electron affinity of the material varies or is tuned based on its stoichiometry, which changes the density of charge carriers at the interface with the TMD material and, therefore, contact resistance (¶0018).
O’Brien differs from claim 17 in that it does not expressly disclose wherein the second insulating layer comprises an insulating material having a band offset of about 200 meV or less with the 2D semiconductor material. However, O’Brien teaches the general conditions of adjusting metal choice and stoichiometry to achieve the desired doping level, Vt shift, and low contact resistance that affect band offset/alignment.
Band-offset/alignment at this interface is thus a result-effective variable that a person of ordinary skill in the art would routinely optimize by adjusting metal choice and stoichiometry to achieve the desired doping level, Vt shift, and low contact resistance (See ¶0018, ¶0026, and ¶0027).
Therefore, a person having ordinary skill in the art before the effective filing date, motivated by the objective to improve the density of charge carriers at the interface with the TMD material and contact resistance would have routinely experimented with known fabrication variables disclosed by O’Brien in order to determine optimal values. Such routine optimization within the general conditions taught by O’Brien would have naturally led to a band offset of about 200 meV or less, as demonstrated by predictable enhancements in the density of charge carriers at the interface and improved contact resistance (reasonable expectation of success given O’Brien’s teachings on parameter effects). See MPEP § 2144.05(II)(“[W]here the general conditions of a claim are disclosed in the prior art, it is not inventive to discover the optimum or workable ranges by routine experimentation” (citing In re Aller, 220 F.2d 454, 456, 105 USPQ 233, 235 (CCPA 1955)).
Re: Claim 18, O’Brien discloses the semiconductor device of claim 16.
O’Brien discloses a metal-oxide doping layer (second insulating layer) formed selectively on TMD extensions outside the channel region (see ¶0018 and ¶0035). This layer induces charge transfer doping by creating a tunable interface (see ¶0018 and ¶0020). Specifically, “the non-stoichiometric metal oxide may be considered a material with a band structure such that the electron affinity of the material varies or is tuned based on its stoichiometry, which changes the density of charge carriers at the interface with the TMD material and, therefore, contact resistance (¶0018).
O’Brien differs from claim 6 in that it does not expressly disclose wherein the second insulating layer comprises an insulating material having a band offset of about 50 meV or greater with the 2D semiconductor material. However, O’Brien teaches the general conditions of adjusting metal choice and stoichiometry to achieve the desired doping level, Vt shift, and low contact resistance that affect band offset/alignment.
Band-offset/alignment at this interface is thus a result-effective variable that a person of ordinary skill in the art would routinely optimize by adjusting metal choice and stoichiometry to achieve the desired doping level, Vt shift, and low contact resistance (See ¶0018, ¶0026, and ¶0027).
Therefore, a person having ordinary skill in the art before the effective filing date, motivated by the objective to improve the density of charge carriers at the interface with the TMD material and contact resistance would have routinely experimented with known fabrication variables disclosed by O’Brien in order to determine optimal values. Such routine optimization within the general conditions taught by O’Brien would have naturally led to a band offset of about 50 meV or greater, as demonstrated by predictable enhancements in the density of charge carriers at the interface and improved contact resistance (reasonable expectation of success given O’Brien’s teachings on parameter effects). See MPEP § 2144.05(II)(“[W]here the general conditions of a claim are disclosed in the prior art, it is not inventive to discover the optimum or workable ranges by routine experimentation” (citing In re Aller, 220 F.2d 454, 456, 105 USPQ 233, 235 (CCPA 1955)).
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure:
KITAMURA et al. (US 20240222461 A1) – Fig. 1 is relevant to the structure of the claimed invention
LIN et al. (US 20240222484 A1) – Fig. 2J is relevant to the structure of the claimed invention
MAXEY et al. (US 20230099814 A1) – Figs. 1B and 1C are relevant to the structure of the claimed invention
Any inquiry concerning this communication or earlier communications from the examiner should be directed to WILLIAM ADROVEL whose telephone number is (571)272-3048. The examiner can normally be reached 7:30 AM - 5:00 PM.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, LEONARD CHANG can be reached at (571) 270-3691. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/WILLIAM ADROVEL/Examiner, Art Unit 2898
/Leonard Chang/Supervisory Patent Examiner, Art Unit 2898
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