Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
DETAILED ACTION
Election/Restrictions
Applicant’s election without traverse of Group I (claims 1-18) in the reply filed on 3/4/26 is acknowledged. Claims [19-20] are withdrawn from further consideration pursuant to 37 CFR 1.142(b) as being drawn to a nonelected invention, there being no allowable generic or linking claim.
Title
The title of the invention is not descriptive. A new title is required that is clearly indicative of the invention to which the claims are directed. (see MPEP § 606.01).
This may result in slightly longer titles, but the loss in brevity of title will be more than offset by the gain in its informative value in indexing, classifying, searching, etc.
The following title is suggested:
“Semiconductor device including Buried Insulating Structure and Nanosheet Transistor Pattern and method for manufacturing the same”
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claims 1 and 10 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Park (US 20220130865).
Regarding claim 1. Fig 4 of Park discloses A semiconductor device comprising:
a substrate 102/103 comprising cell regions (the region between 120_1 and 120_2 and the region between 130_1 and 130_2), a dummy region (the region 120_2/130_1, which is fin-cut region [0023]. Thus, being dummy region) between the cell regions, an upper surface (the upper surface of 103) and a lower surface (bottom surface of 102) opposite the upper surface in a first direction (DR3);
an active pattern (111/NW1/NW2/112) disposed on the upper surface of the substrate,
the active pattern comprising a lower pattern 111/112 extending in a second direction (DR1) crossing the first direction and a plurality of sheet patterns (NW1/NW2) spaced apart from each other in the first direction, the plurality of sheet patterns being disposed in the cell region (Fig 4);
a plurality of gate structures (121/122 in 120 and 131/132 in 130) spaced apart from each other in the second direction on the lower pattern, the plurality of gate structures comprising a gate electrode 121/131 [0047]/[0078] and a gate insulating layer 122/132 [0047]/[0078], the gate electrode and the gate insulating layer surrounding the sheet patterns (Fig 4);
a source/drain pattern 141/142 [0023] disposed between the gate structures adjacent to each other; and
a buried insulating pattern 150/205 [0022]/[0092] penetrating the substrate and the lower pattern in the dummy region (Fig 4),
wherein the buried insulating pattern comprises a first surface (the bottom surface of 205) and a second surface (the top surface of 150) opposite to each other in the first direction, the first surface of the buried insulating pattern is placed on the same plane as the lower surface of the substrate (Fig 4, [0092]: refer to the 205a, which is coplanar with the bottom surface of 102), and
the second surface of the buried insulating pattern is higher than the upper surface of the substrate (Fig 4: refer to the top surface of 150).
Regarding claim 10. Fig 4 of Park discloses A semiconductor device comprising:
a substrate 102/103 comprising a cell region (the region between 120_1 and 120_2 and the region between 130_1 and 130_2), a dummy region (the region 120_2/130_1, which is fin-cut region [0023]. Thus, being dummy region) adjacent to the cell region, an upper surface (the upper surface of 103) and a lower surface (bottom surface of 102) opposite the upper surface in a first direction (DR3);
an active pattern (111/NW1/NW2/112) disposed on the upper surface of the substrate,
the active pattern comprising a lower pattern 111/112 extending in a second direction (DR1) crossing the first direction and a plurality of sheet patterns spaced apart from each other in the first direction,
the plurality of sheet patterns (NW1/NW2) being disposed in the cell region;
a plurality of gate structures (121/122 in 120 and 131/132 in 130) spaced apart from each other in the second direction on the lower pattern,
the plurality of gate structures comprising a gate electrode 121/131 [0047]/[0078] and a gate insulating layer 122/132 [0047]/[0078], the gate electrode and the gate insulating layer surrounding the sheet patterns (Fig 4);
a source/drain pattern 141/142 disposed between the gate structures adjacent to each other; and
a buried insulating pattern 150/205 penetrating the substrate and the lower pattern in the dummy region (Fig 4),
wherein the buried insulating pattern comprises a first (the bottom surface of 205) and a second surface (the top surface of 150) opposite to each other in the first direction,
the first surface of the buried insulating pattern is on the same plane as the lower surface of the substrate (Fig 2, [0092]: refer to the 205a, which is coplanar with the bottom surface of 102), and
the second surface of the buried insulating pattern is higher than the upper surface of the substrate (Fig 4: refer to the top surface of 150).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 2-4 and 11-13 are rejected under 35 U.S.C. 103 as being unpatentable over Park (US 20220130865) in view of Lim (US 20210036121).
Regarding claim 2. Park discloses The semiconductor device of claim 1, wherein the active pattern is not disposed on the dummy region (Fig 4).
But Park does not disclose the gate structures are not disposed on the dummy region.
However, Fig 2 of Lim discloses the gate structures 162/165 [0034] are not disposed on the dummy region (SR).
Thus, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the Park’s device to have Lim’s structure for the purpose of providing effective elimination sub-channel leakage currents by separating the channel from the substrate, which is crucial for reducing off-state power consumption.
Regarding claim 3. Park in view of Lim discloses The semiconductor device of claim 2, Park discloses further comprising a field insulating layer (the left 124 directly contacting left side of 150, and 134 directly contacting right side of 150) between two lower patterns adjacent to each other (Fig 4).
Regarding claim 4. Park in view of Lim discloses The semiconductor device of claim 3, Park discloses wherein an upper surface of the field insulating layer and an upper surface of the buried insulating pattern are on the same plane (Fig 4).
Regarding claim 11. Park discloses The semiconductor device of claim 10, the active pattern is not disposed on the dummy region (Fig 4).
But Park does not disclose the gate structures are not disposed on the dummy region.
However, Fig 2 of Lim discloses the gate structures 162/165 [0034] are not disposed on the dummy region (SR).
Thus, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the Park’s device to have Lim’s structure for the purpose of providing effective elimination sub-channel leakage currents by separating the channel from the substrate, which is crucial for reducing off-state power consumption.
Regarding claim 12. Park in view of Lim discloses The semiconductor device of claim 11, Park discloses further comprising a field insulating layer (the left 124 directly contacting left side of 150, and 134 directly contacting right side of 150) between lower patterns adjacent to each other (Fig 4).
Regarding claim 13. Park in view of Lim discloses The semiconductor device of claim 12, Park discloses wherein an upper surface of the field insulating layer and an upper surface of the buried insulating pattern are on the same plane (Fig 4).
Claims 5-9 and 14-18 are rejected under 35 U.S.C. 103 as being unpatentable over Park (US 20220130865) in view of Huang (US 20210375857).
Regarding claim 5. Park discloses The semiconductor device of claim 1. But Park does not disclose wherein the source/drain pattern comprises a source/drain blocking layer and a source/drain filling layer disposed on the source/drain blocking layer.
However, Fig 21B of Huang discloses the source/drain pattern comprises a source/drain blocking layer 230 [0035] and a source/drain filling layer 240 disposed on the source/drain blocking layer.
Thus, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the park’s device to have the Huang’s source/drain structure for the purpose of providing enhanced current leakage characteristics between source/drain and substrate with undoped epitaxial structure between doped source/drain filling layer and substrate [0035].
Regarding claim 6. Park discloses The semiconductor device of claim 1. But Park does not disclose further comprising a backside wiring line disposed on the lower surface of the substrate.
However, Fig 21B of Huang discloses a backside wiring line 374 disposed on the lower surface of the substrate 330.
Thus, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the Park’s device to have the Huang’s backside wiring for the purpose of providing enhanced power delivery from the top side of the wafer to the bottom, which resolving severe interconnect congestion while significantly boosting performance. Thereby, providing more stable power to the transistor.
Regarding claim 7. Park in view of Huang discloses The semiconductor device of claim 6, Huang discloses further comprising a source/drain contact 270/280 [0047] disposed on the upper surface of the substrate, and electrically connected to the source/drain pattern (Fig 21B, [0047]).
Thus, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the Park’s device to have the Huang’s frontside source/drain contact for the purpose of providing reduced parasitic resistance and capacitance typically associated with stacked channels when scaling to smaller nodes.
Regarding claim 8. Park in view of Huang discloses The semiconductor device of claim 7, Huang discloses further comprising:
a front wiring via 292 electrically connected to the source/drain contact; and
a front wiring plug 372 electrically connected to the front wiring via (Fig 21B).
Regarding claim 9. Park in view of Huang discloses The semiconductor device of claim 6, Huang discloses further comprising a source/drain contact 360 [0057] penetrating the substrate and disposed between the backside wiring line and the source/drain pattern (Fig 21B).
Regarding claim 14. Park discloses The semiconductor device of claim 10. But Park does not disclose wherein the source/drain pattern comprises a source/drain blocking layer and a source/drain filling layer disposed on the source/drain blocking layer.
However, Fig 21B of Huang discloses the source/drain pattern comprises a source/drain blocking layer 230 [0035] and a source/drain filling layer 240 disposed on the source/drain blocking layer.
Thus, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the park’s device to have the Huang’s source/drain structure for the purpose of providing enhanced current leakage characteristics between source/drain and substrate with undoped epitaxial structure between doped source/drain filling layer and substrate [0035].
Regarding claim 15. Park discloses The semiconductor device of claim 10. But Park does not disclose further comprising a backside wiring line disposed on the lower surface of the substrate.
However, Fig 21B of Huang discloses a backside wiring line 374 disposed on the lower surface of the substrate 330.
Thus, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the Park’s device to have the Huang’s backside wiring for the purpose of providing enhanced power delivery from the top side of the wafer to the bottom, which resolving severe interconnect congestion while significantly boosting performance. Thereby, providing more stable power to the transistor.
Regarding claim 16. Park in view of Huang discloses The semiconductor device of claim 15, Huang discloses further comprising a source/drain contact 270/280 [0047] disposed on the upper surface of the substrate, and electrically connected to the source/drain pattern (Fig 21B, [0047]).
Regarding claim 17. Park in view of Huang discloses The semiconductor device of claim 16, Huang discloses further comprising:
a front wiring via 292 electrically connected to the source/drain contact; and
a front wiring plug 372 electrically connected to the front wiring via (Fig 21B).
Regarding claim 18. Huang discloses The semiconductor device of claim 15, Huang discloses further comprising a source/drain contact 360 [0057] penetrating the substrate and disposed between the backside wiring line and the source/drain pattern (Fig 21B).
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to Changhyun Yi whose telephone number is (571)270-7799. The examiner can normally be reached Monday-Friday: 8A-4P.
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/Changhyun Yi/Primary Examiner, Art Unit 2812
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