Detailed Action
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claim(s) 1, 4-5 and 9-10 is/are rejected under 35 U.S.C. 102(a)(1)/102(a)(2) as being anticipated by Kim et. Al. (US 20220359341 A1 hereinafter Kim).
Regarding claim 1, Kim teaches in Figs. 2-3 with associated text a semiconductor device, comprising: a substrate 252 including a dielectric layer (290 or 320 for example [0047], [0077]) and a semiconductor layer (250 including 252) on the dielectric layer (Fig. 2, [0051]); a first electrode 254 laterally surrounding a first region (region inside 254 Fig. 3, [0054]) of the semiconductor layer; a second region (region of 252 outside 254 of the semiconductor layer laterally surrounding and contacting the first electrode (see annotated Fig. below); and a second electrode 256 laterally surrounding and contacting the second region of the semiconductor layer (Fig. 3, [0055]).
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574
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Regarding claim 4, Kim teaches the first electrode extends from a plane coplanar with a surface (surface interfaceing 254 of the semiconductor layer to the dielectric layer (here the dielectric layer is interpreted to be 290) (Fig. 5); and the first electrode includes a conductive material surrounding the first region of the semiconductor layer (Fig. 3).
Regarding claim 5, Kim teaches the conductive material includes at least one of silicide, tungsten, aluminum, copper, titanium, and tantalum ([0061]).
Regarding claim 9, Kim teaches the second electrode extends from a plane coplanar with a surface (surface interfacing 256) of the semiconductor layer to the dielectric layer (here the dielectric layer is interpreted to be 290) (Fig. 5); and the second electrode includes a conductive material contacting the second region of the semiconductor layer (Fig. 3).
Regarding claim 10, Kim teaches the conductive material includes at least one of silicide, tungsten, aluminum, copper, titanium, and tantalum ([0061]).
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102 of this title, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 2 are rejected under 35 U.S.C. 103 as being unpatentable over Kim as applied to claim 1 and further in view of Luo et. Al. (Luo, Jiajian, Jung‐Youn Lim, Archana Venugopal, Jingjing Chen, Zongqing Ren and Jaeho Lee. “Dynamic Thermal Management of Power Transistors using Holey Silicon-Based Thermoelectric Cooling.” 2022 21st IEEE Intersociety Conference on Thermal and Thermomechanical Phenomena in Electronic Systems (iTherm) (2022): 1-7.).
Regarding claim 2, Kim teaches the semiconductor device of claim 1.
Kim does not specify the first region of the semiconductor layer includes one or more semiconductor components generating heat during operation.
Luo discloses in Figs. 1-2 with associated text a first region (a in Fig. 1) of the semiconductor layer includes one or more semiconductor components generating heat during operation (power transistor page 2, right column 1st paragraph).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to use a structure similar to that of Luo in the device of Kim because according to Luo such a structure provides an efficient hotspot cooling solution under transient heating conditions for power transistors, holey silicon as an ideal thermoelectric material provides both compatibility and high cooling performance. This system is integrated on the side of a power transistor to provide active cooling for local hotspots under dynamic hotspot conditions (Abstract).
Claims 3 is rejected under 35 U.S.C. 103 as being unpatentable over Kim in view of Luo as applied to claim 2 and further in view of Hiroshi et. Al. (US 20020014639 A1 hereinafter Hiroshi).
Regarding claim 3, Kim teaches the semiconductor device of claim 2.
Kim does not specify the one or more semiconductor components include a laterally-diffused metal-oxide-semiconductor (LDMOS) transistor however Kim discloses it is a power transistor.
Hiroshi discloses a power transistor that is a LDMOS transistor [0021].
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to use a structure similar to that of Hiroshi for the power transistor of Kim in view of Luo because according to Hiroshi LDMOS transistor are suitable as power transistors [0021] furthermore using an LDMOS transistor for a power transistor would have been very well known to one of ordinary skill in the art before the effective filing date.
Claims 6-7 are rejected under 35 U.S.C. 103 as being unpatentable over Kim as applied to claim 1 and further in view of Kim et. Al. (US 20190287877 A1 hereinafter hereinafter Kim877).
Regarding claim 6, Kim teaches the semiconductor device of claim 1, wherein the second region of the semiconductor layer includes a plurality of cavities (holes [0051])..
Kim does not specify each cavity of the plurality extended from a plane coplanar with a surface of the semiconductor layer to the dielectric layer
Kim877 discloses in Figs. 1-2 with associated text a semiconductor layer 101 similar to that of Kim wherein each cavity 103c of the plurality extended from a plane 101a coplanar with a surface of the semiconductor layer to a dielectric layer 113 (Fig. 1, [0020] and [0022])
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to use holes similar to those of Kim877 for those of Kim because according to Kim877 the first electrode 107a may decrease in temperature, and the second electrode 107b may increase in temperature. In contrast, when the first voltage is less than the second voltage, the first electrode 107a may increase in temperature and the second electrode 107b may decrease in temperature, while the first, second, and third holes 103a, 103b, and 103c may have an adiabatic function to prevent heat transfer therethrough between the first electrode 107a and the second electrode 107b ([0024]).
Regarding claim 7, Kim in view of Kim877 teaches one or more cavities of the plurality of cavities has a footprint of a circle, a rectangle, or an obround shape (circle (Fig. 2).
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to AARON J GRAY whose telephone number is (571)270-7629. The examiner can normally be reached Monday-Friday 9am-4pm.
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/AARON J GRAY/Examiner, Art Unit 2897
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