DETAILED ACTION
Response to Arguments
Applicant’s arguments with respect to claim(s) 1 and 11 have been considered but are moot in view of the new grounds of rejection detailed below.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-5 are rejected under 35 U.S.C. 103 as being obvious over JEONG et al. (US 20210183859 A1, see IDS dated 11/01/2024), hereinafter “Jeong,” in view of CHU et al. (US 20240120256 A1), hereinafter “Chu.”
Re: Claim 1, Jeong discloses an integrated circuit comprising (See Fig. 2):
a plurality of gate electrodes including (Fig. 2: GL1a, GL2a, GL1b, GL2b)
a first gate electrode and a second gate electrode being apart in a first direction (Fig. 2: GL1a and GL2a are apart in the X-direction), and
a third gate electrode and a fourth gate electrode being apart in the first direction (Fig. 2: GL1b and GL2b are apart in the X-direction),
wherein the second gate electrode and the third gate electrode are configured to receive a first control signal (Fig. 2: GL2a and GL1b; ¶0030: A first control signal A may be applied to the second gate pattern GL1b and the third gate pattern GL2a through the second and third gate contacts CB1b and CB2a.), and
the first gate electrode and the fourth gate electrode are configured receive a second control signal (Fig. 2: GL1a and GL2b; ¶0030: A second control signal B may be applied to the first gate pattern GL1a and the fourth gate pattern GL2b through the first and fourth gate contacts CB1a and CB2b.);
a plurality of drain regions comprising (¶0007: a plurality of source/drain regions spaced apart from each other in the first direction on the first and second active regions)
a first drain region between the first gate electrode and the second gate electrode (Fig. 1: drain of the first NMOS transistor NM1 connected to output node ND; See Fig. 2; ¶0022: The first PMOS transistor PM1 may have a source connected to a first voltage terminal V1, a gate for receiving a first control signal A, and a drain connected to an output node ND. The first NMOS transistor may have a drain connected to an output node ND, a gate for receiving a second control signal B; ¶0059: the source/drain region in the first active region AR1 between the first and second gate lines GL1 and GL2, i.e., between GL1a and GL2a, on which common contact line CAO is disposed), and
a second drain region between the third gate electrode and the fourth gate electrode (Fig. 1: drain of the second PMOS transistor PM2 connected to output node ND; see Fig. 2; ¶0022: The second PMOS transistor may have a source connected to a third voltage terminal V3, a gate for receiving the second control signal B, and a drain connected to the output node ND. The second NMOS transistor NM2 may have a drain connected to the output node ND, a gate for receiving the first control signal A, and a source connected to a fourth voltage terminal V4; ¶0059: the source/drain region in the second active region AR2 between the first and second gate lines GL1 and GL2, i.e., between GL1b and GL2b, to which common contact line CAO is extends),
wherein the first drain region and the second drain region are configured to be electrically connected to each other (Fig. 1: output node ND; ¶0059: the common contact line CAO may connect the first active region AR1 and the second active region AR2 to each other; ¶0077: The common contact line CAO may be disposed on the source/drain region S/D of the plurality of source/drain regions S/D disposed among the first to fourth gate patterns GL1a, GL1b, GL2a, and GL2b. The common contact line CAO may extend in the second direction Y, and may overlap the first active region AR1, the second active region AR2, and the isolation region IR.);
a front-side wiring layer disposed above the plurality of gate electrodes in a vertical direction and connected to at least one of the plurality of drain regions and the plurality of gate electrodes (Fig. 2: first and second wiring structures DS1 and DS2 disposed above the gate electrodes in a vertical direction-Z and connected to the gate electrodes through gate contact CB1a, CB1b, CB2a and CB2b; ¶0062: The fifth lower wiring layer M15 for the output node ND may be connected to the common contact line CAO; Figs. 5A and 5B show front side wiring layers disposed above gate electrodes Fig. 6 shows front side wiring layers above gate electrodes which contact drain regions; ¶0076: an active contact CA may penetrate the lowermost interlayer insulating film toward the source/drain region S/D; ¶0077: The common contact line CAO may be disposed on the source/drain region S/D of the plurality of source/drain regions S/D disposed among the first to fourth gate patterns GL1a, GL1b, GL2a, and GL2b.); and
Jeong further teaches that the wiring for the output node ND is disposed over the isolation region IR between the first and second active regions, i.e., laterally offset from the drain regions in a plan view (¶0062: The fifth lower wiring layer M15 for the output node ND may be connected to the common contact line CAO and may overlap the isolation region IR. Accordingly, a cross-coupled structure having a reduced cell height may be implemented).
However, Jeong does not disclose a backside wiring layer disposed under the plurality of gate electrodes in the vertical direction and connected to at least another one of the plurality of drain regions and the plurality of gate electrodes, wherein, in a plan view, the backside wiring layer is laterally offset from the plurality of drain regions.
In a similar field of endeavor, Chu discloses a backside wiring layer disposed under the plurality of gate electrodes in the vertical direction (Figs. 1-1 to 1-3: backside local signal lines 112, 114, 116, 117 formed on the backside of the device, on the opposite side of gates 124 from the frontside BEOL; see ¶0030 and ¶¶0052-0053) and
connected to at least another one of the plurality of drain regions and the plurality of gate electrodes (¶0030: Backside local signal lines (112, 114, 116) of the semiconductor device 100 connect to the source/drain epitaxy or gate (124) through a backside contact (126).; Fig. 1-2: local signal line 116 connected to two gates 124 through backside gate contacts nCB 126; Fig. 1-3 and Fig. 18C: local signal line 117 connected to source/drain regions through backside source/drain contacts nCA; ¶0027: local signal lines for both gate connection and source/drain (S/D) connection), wherein, in a plan view, the backside wiring layer is laterally offset from the plurality of drain regions (¶0028: forming backside local signal lines to backside contacts between the backside power rails, or at N2P spaces; ¶0053: The local signal lines (112, 114, 116) are between the N2P spaces (105).; Fig. 16D (plan view): N2P spaces 105, labeled “SIGNALS BETWEEN N2P,” lie between the NFET rows and the PFET rows; Fig. 1-1: local signal line 112 located in N2P space 105 between N channel FET region 506 and P channel FET region 508. The source/drain epitaxies 906 are formed in the transistor rows: Fig. 9C shows cut X2 running through a PFET row; Figs. 15C-15D likewise show backside source/drain contacts 1504 on the source/drain epitaxy within the NFET and PFET rows, see ¶0051. Thus the local signal lines in the N2P spaces 105 do not overlap the source/drain regions in plan view).
Therefore, it would have been obvious to a person having ordinary skill in the art before the effective filing date of the current application to have modified the structure disclosed by Jeong to include a backside wiring layer located between the first and second active regions and connected to the drain regions and/or gate electrodes through backside contacts, as disclosed by Chu, in order to reduce the high resistance bottleneck of output nodes connected through tight-pitch front-side metals and vias as cell height is reduced (See Chu, ¶0031), and to provide local signal routing for both gate and source/drain connections in addition to backside power (See Chu, ¶0027). Jeong already seeks to reduce the number of lower wiring tracks and cell height of the cross-coupled structure by routing the output node over the isolation region between the active regions (See Jeong, ¶0060-0062), and Chu places its backside local signal lines in that same region between the N channel and P channel regions. The modification is the use of a known technique to improve a similar device in the same way. See KSR Int’l Co. v Teleflex Inc., 550 U.S. 398, 417 (2007).
Re: Claim 2, the combination of Jeong in view of Chu discloses the integrated circuit of claim 1.
Jeong also discloses further comprising a first active region and a second active region (Fig. 2: AR1 and AR2), each of which extends in the first direction and is apart in a second direction perpendicular to the first direction (Fig. 2: AR1 and AR2 extend in the X-direction and are separated/apart by an isolation region (IR) along a perpendicular direction-Y),
wherein each of the first gate electrode and the second gate electrode extends in the second direction above the first active region (Fig. 2: GL1a and GL2a have a gate structure which extends in the Y-direction, i.e., second direction above active region AR1), and
each of the third gate electrode and the fourth gate electrode extends in the second direction above the second active region (Fig. 2: GL1b and GL2b have a gate structure which extends in the Y-direction, i.e., second direction above active region AR2).
Re: Claim 3, the combination of Jeong in view of Chu discloses the integrated circuit of claim 1.
Jeong also discloses further comprising:
a first active region and a second active region, each of which extends in the first direction and is apart in a second direction perpendicular to the first direction (Fig. 2: AR1 and AR2 extend in the X-direction and are apart in the Y-direction, separated by isolation region IR); and
a ... contact connected to the first drain region and the second drain region and extending between the first active region and the second active region in the second direction (¶0059: A common contact line or a common contact pad CAO may be disposed in the first active region AR1 between the first and second gate lines GL1 and GL2, and the common contact pad CAO may extend in the second direction Y and may extend to the second active region AR2... For example, the common contact line CAO may connect the first active region AR1 and the second active region AR2 to each other; ¶0077: The common contact line CAO... may overlap the first active region AR1, the second active region AR2, and the isolation region IR.), ...
Jeong’s common contact line CAO is a front-side contact. Jeong does not disclose that the contact is a ... backside contact, wherein the first drain region and the second drain region are connected to the backside wiring layer through the backside contact.
Chu discloses connecting source/drain regions to the backside wiring layer through ... backside contact, wherein the first drain region and the second drain region are connected to the backside wiring layer through the backside contact (¶0030: Backside local signal lines (112, 114, 116) of the semiconductor device 100 connect to the source/drain epitaxy or gate (124) through a backside contact (126).; ¶0051 and Fig. 15C: backside to source/drain contacts (1504) formed... to contact the source/drains (906); Fig. 1-3: backside source/drain contacts nCA connecting source/drain regions to local signal line 117 along cut X3, which Fig. 18D shows between the PFET and NFET rows, see ¶0056).
Therefore, it would have been obvious to a person having ordinary skill in the art before the effective filing date of the current application to have formed Jeong’s common contact line CAO, which connects the drain regions of the first and second active region across the isolation region, as a backside contact connected to Chu’s backside local signal line in the space between the active regions, so that the first and second drain regions are connected to the backside wiring layer through the backside contact. This would have allowed the output node ND to be carried by the backside wiring instead of front-side M0 tracks and vias, reducing the output-node resistance bottleneck (See Chu, ¶0031, ¶0033: a larger via results in lower resistance and improved performance) while preserving Jeong’s connection of the two active regions without additional front-side wiring layers (See Jeong, ¶0059).
Re: Claim 4, the combination of Jeong in view of Chu discloses the integrated circuit of claim 3.
Jeong also discloses further comprising contacts respectively disposed on the plurality of gate electrodes (Fig. 2: CB1a/b, CB2a/b contacts disposed on gate electrodes GL1a/b and GL2a/b),
wherein the front-side wiring layer comprises front-side wiring patterns respectively disposed on the contacts (Fig. 2: first and second wiring structures DS1/DS2 disposed on said contacts), and at least one of the plurality of gate electrodes is connected to a corresponding front-side wiring pattern through a corresponding one of the contacts (Fig. 2: DS1/DS2 connected to contacts CB1a/b, CB2a/b disposed on gate electrodes GL1a/b and GL2a/b).
Re: Claim 5, the combination of Jeong in view of Chu discloses the integrated circuit of claim 3.
Jeong also discloses further comprising a first contact disposed on the first gate electrode (Fig. 2: CB1a disposed on GL1a),
a second contact disposed on the second gate electrode (Fig. 2: CB2a disposed on GL2a),
a third contact disposed on the third gate electrode (Fig. 2: CB1b disposed on GL1b), and a fourth contact disposed on the fourth gate electrode (Fig. 2: CB2b disposed on GL2b),
wherein the front-side wiring layer includes a first front-side wiring pattern disposed on the first contact (Fig. 2: DS1 wiring pattern disposed on contact CB1a via M11, V1, M21, M31),
a second front-side wiring pattern disposed on the second contact (Fig. 2: DS2 wiring pattern disposed on contact CB2a via M13, V1, M23, V2, M32),
a third front-side wiring pattern disposed on the third contact (Fig. 2: DS2 wiring pattern disposed on contact CB1b via M14, V1, M24, V2, M32), and
a fourth front-side wiring pattern disposed on the fourth contact (Fig. 2: DS1 wiring pattern disposed on contact CB2b via M12, M22, M31), and
the first gate electrode is connected to the first front-side wiring pattern through the first contact (Fig. 2: GL1a connected to DS1 wiring pattern through CB1a),
the second gate electrode is connected to the second front-side wiring pattern through the second contact (Fig. 2: GL2a connected to DS2 wiring pattern through CB2a),
the third gate electrode is connected to the third front-side wiring pattern through the third contact (Fig. 2: GL1b connected to DS2 wiring pattern through CB1b), and
the fourth gate electrode is connected to the fourth front-side wiring pattern through the fourth contact (Fig. 2: GL2b connected to DS1 wiring pattern through CB2b).
Claims 11-13, 16 and 17 are rejected under 35 U.S.C. 103 as being obvious over DO et al. (US 20180226323 A1), hereinafter “Do,” in view of CHU et al. (US 20240120256 A1).
Re: Claim 11, Do discloses an integrated circuit comprising (See Figs. 2A and 8-10):
a first active region extending in a first direction (Fig. 2A and 8: first active region AR1 extends in the X-direction; ¶0055: The first and second active regions AR1 and AR2 may extend in a first direction (e.g., maybe elongated in a first direction corresponding to the X direction in the figures));
a source region and a drain region of the first active region, the source region and the drain region being spaced apart from each other in the first direction (Fig. 2A and 8: the regions of AR1 on both sides of the first gate line GL1, spaced apart in the X-direction; ¶0060: The first conductive pattern PT1 may electrically connect regions on both sides of the first gate line GL1 in the first active region AR1.; ¶0077 and Fig. 8: first contacts CA may be respectively arranged between two adjacent gate lines GL in a first active region AR1, i.e., on the source/drain regions on either side of GL1.);
a first dummy gate electrode extending in a second direction perpendicular to the first direction, between the source region and the drain region (Figs. 2A and 8: first gate line GL1 extends in the Y-direction between said regions; ¶0056: Each of the gate lines GL may extend in the second direction; ¶0060: Accordingly, the first gate line GL1 may be a dummy gate line, that is, a skipped gate line, which is not a real gate line.);
Do further discloses that the source region and the drain region are electrically connected to each other across the dummy gate electrode, and thus receive the same voltage, through first contacts CA respectively connected to them and a contact jumper CJ1 connected to a wiring layer (¶0054: the term “contact jumper” refers to a conductor having a relatively short length connecting any two points or two terminals in the integrated circuit 10; ¶0078 and Fig. 8: the third contact CM may correspond to a merge contact and may merge the first contacts CA spaced apart from each other... A via V0 may be arranged on the third contact CM in a middle region MR.).
However, Do implements the contacts and the contact jumper on the front side of the substrate and does not disclose first backside contacts disposed under the source region and the drain region in a vertical direction and respectively connected to the source region and the drain region; and a backside wiring layer connected to the first backside contacts, wherein the source region and the drain region are configured to receive a same voltage from the backside wiring layer through the first backside contacts.
In a similar field of endeavor, Chu discloses first backside contacts disposed under the source region and the drain region in a vertical direction and respectively connected to the source region and the drain region (¶0051 and Fig. 15C: backside source/drain contacts (1504), labeled nCA, formed within the backside interlayer dielectric 1402 and bottom dielectric isolation 802 to contact the source/drains (906), i.e., directly on the backside of the source/drain epitaxy after the wafer is flipped, see ¶0048; Fig. 15D: backside source/drain contacts 1504 located within the NFET and PFET rows, under the source/drain regions on both sides of a gate line; ¶0095: nCA backside contact to source/drain); and
a backside wiring layer connected to the first backside contacts (¶0030: Backside local signal lines (112, 114, 116) of the semiconductor device 100 connect to the source/drain epitaxy or gate (124) through a backside contact (126); ¶0059: The backside power rails may connect to source/drain epitaxies through backside contacts; Fig. 1-3: local signal line 117 connected to two backside source/drain contacts nCA)),
wherein the source region and the drain region are configured to receive a same voltage from the backside wiring layer through the first backside contacts (Fig. 1-3: the two backside source/drain contacts nCA, spaced apart in the X-direction with gate lines therebetween, are both connected to the same local signal line 117, so the source/drain regions they contact are at the same potential; see also Fig. 18C, the same cut X3 in ¶0056; ¶0027: local signal lines for both gate connection and source/drain (S/D) connection; ¶0002: a backside source/drain supply voltage (VDD) and source/drain supply voltage (VSS)).
Therefore, it would have been obvious to a person having ordinary skill in the art before the effective filing date of the current application to have modified the structure disclosed by Do to connect the source region and the drain region on both sides of the dummy gate electrode through first backside contacts to a backside wiring layer, as disclosed by Chu, instead of through front-side contacts and a front-side jumper, in order to free front-side routing tracks and reduce the resistance bottleneck of front-side metals and vias as standard cell heigh is reduced (See Chu, ¶0031). Do addresses the same problem of limited front-side tracks and congestion in the middle region of reduced-height standard cells (see Do, ¶0052 and ¶¶0058-0059), and Chu teaches that source/drain-to-source/drain local interconnections may be made on the backside (Chu, ¶0027, Fig. 1-3). The modification is the use of a known technique to improve a similar device in the same way. See KSR Int’l Co. v Teleflex Inc., 550 U.S. 398, 417 (2007).
Re: Claim 12, the combination of Do in view of Chu discloses the integrated circuit of claim 11.
Chu further discloses wherein the backside wiring layer extends in the first direction (¶0030 and ¶0059: a cell architecture with the backside local signal lines running horizontally on a backside, and a frontside metal running vertically; Fig. 1-3: local signal line 117 shown in cut X3; ¶0056 and Fig. 18D: cut X3 extends in the X-direction, parallel to the NFET and PFET rows).
Therefore, it would have been obvious to a person having ordinary skill in the art before the effective filing date of the current application to have modified the structure disclosed by Do to include a backside wiring layer extending in the first direction as disclosed by Chu, for the reasons given for claim 11 and because a line running parallel to the active region spans the source and drain regions on both sides of the dummy gate electrode.
Re: Claim 13 the combination of Do in view of Chu discloses the integrated circuit of claim 11.
Do also discloses further comprising ... vias respectively connected to the first ... contacts (Fig. 21B: first vias V0 on respective first contacts CA in the first active region AR1, the first contacts CA being on source/drain regions spaced apart in the X-direction; ¶0114: The first vias V0 may be part of a first layer of vias arranged on the layer of contacts including the first contacts CA and second contacts CB.), wherein the source region and the drain region are configured to receive the same voltage from the ... wiring layer through the first ... contacts and the ... vias (Fig. 21B: the first vias V0 in AR1 are all connected to the same first metal pattern M1a, so the source/drain regions below them are at the same potential; ¶0115: The first metal layer M1 may include a first metal pattern M1a connecting first vias V0 arranged in a first active region AR1 to each other).
However, Do discloses front-side vias, contacts and wiring, and does not disclose ... backside vias.
Chu further discloses first backside contacts respectively connected to the source/drain regions (0051 and Fig. 15C: backside to source/drain contacts (1504), labeled nCA, formed to contact the source/drains (906)) and a backside wiring layer connected to the source/drain regions through the backside contacts so that they receive the same voltage (See ¶0030 and ¶0059; Fig. 1-3: two backside source/drain contacts nCA connected to the same local signal line 117). Chu further discloses backside vias connecting backside conductive levels to one another (¶0054 and Fig. 17A: Vias (1706) are formed within the backside interlayer dielectric 1702 to join the power rails (106, 110) to the formed backside power distribution network (1704)).
Therefore, it would have been obvious to a person having ordinary skill in the art before the effective filing date of the current application, when relocating Do’s contact, via and wiring connection to the backside as set forth for claim 11, to include backside vias respectively connected to the first backside contacts, wherein the source region and the drain region are configured to receive the same voltage from the backside wiring layer through the first backside contacts and the backside vias, because Do places a via on each contact below the common wiring patterns (See Do, ¶¶0114-0115, Fig. 21B) and Chu uses vias to connect backside conductive levels (Chu, ¶0054, Fig. 17A). Doing so merely carries Do’s know contact-via-wiring stack over to the backside wiring levels of Chu, with predictable results. See KSR, 550 U.S. at 416.
Re: Claim 16 the combination of Do in view of Chu discloses the integrated circuit of claim 11.
Do also discloses a conductor connected to the contacts on both source/drain regions and extending in the first direction, through which the regions are connected to the wiring layer (Fig. 8: third contact CM, whose first conductive pattern PT1 extends in the X-direction across GL1 and overlaps both first contacts CA, with via V0 on the third contact CM; ¶0078: the third contact CM may correspond to a merge contact and may merge the first contacts CA spaced apart from each other. The third contact CM may be arranged above the first contacts CA ... A via V0 may be arranged on the third contact CM in a middle region MR.). The combination therefore discloses further comprising a backside via connected to the first backside contacts and extending in the first direction, wherein the source region and the drain region are configured to receive the same voltage from the backside wiring layer through the first backside contacts and the backside via.
Therefore, it would have been obvious to a person having ordinary skill in the art before the effective filing date of the current application, when implementing Do’s contact jumper on the backside as set forth for claim 11, to form the merging conductor as a backside via extending in the first direction between the first backside contacts and the backside wiring layer, in order to merge the two backside contacts with a single interconnect as Do does on the front side (See Do, ¶¶0077-0078 and Fig. 8)
Re: Claim 17 the combination of Do in view of Chu discloses the integrated circuit of claim 11.
Do also discloses further comprising:
a second gate electrode apart from the first dummy gate electrode (Figs. 2A and 8: second gate line GL2 spaced apart from the first gate line GL1 in the X-direction; 0056: the gate lines GL may be spaced apart from each other at regular intervals in the first direction); and
a front-side wiring layer disposed above the second gate electrode in the vertical direction (Fig. 21B and ¶¶0114-0115: first metal layer M1 disposed on the first layer of vias above the gate lines GL). Chu likewise discloses frontside metal M1 above the gates 124 (See Figs. 1-2 and 1-3).
Conclusion
THIS ACTION IS MADE FINAL. Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to WILLIAM ADROVEL whose telephone number is (571)272-3048. The examiner can normally be reached 7:30 AM - 5:00 PM.
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/WILLIAM ADROVEL/Examiner, Art Unit 2898
/Leonard Chang/Supervisory Patent Examiner, Art Unit 2898
