DETAILED ACTION
Election/Restrictions
Claims 6-10, 14-15, and 18-20 are withdrawn from further consideration pursuant to 37 CFR 1.142(b), as being drawn to a nonelected species, there being no allowable generic or linking claim. Applicant timely traversed the restriction (election) requirement in the reply filed on 03/20/2026.
Priority
Receipt is acknowledged of certified copies of papers required by 37 CFR 1.55.
Information Disclosure Statement
The information disclosure statements (IDS) submitted on 12/27/2023 and 02/02/2024 are in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statement is being considered by the examiner.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-5 and 11-13, 16 and 17 are rejected under 35 U.S.C. 103 as being obvious over JEONG et al. (US 20210183859 A1, see IDS dated 11/01/2024), hereinafter “Jeong,” in view of MIAO et al. (US 20240105617 A1), hereinafter “Miao.”
The applied reference has a common assignee with the instant application. Based upon the earlier effectively filed date of the reference, it constitutes prior art under 35 U.S.C. 102(a)(2).
This rejection under 35 U.S.C. 103 might be overcome by: (1) a showing under 37 CFR 1.130(a) that the subject matter disclosed in the reference was obtained directly or indirectly from the inventor or a joint inventor of this application and is thus not prior art in accordance with 35 U.S.C.102(b)(2)(A); (2) a showing under 37 CFR 1.130(b) of a prior public disclosure under 35 U.S.C. 102(b)(2)(B); or (3) a statement pursuant to 35 U.S.C. 102(b)(2)(C) establishing that, not later than the effective filing date of the claimed invention, the subject matter disclosed and the claimed invention were either owned by the same person or subject to an obligation of assignment to the same person or subject to a joint research agreement. See generally MPEP § 717.02.
Re: Claim 1, Jeong discloses an integrated circuit comprising (See Fig. 2):
a plurality of gate electrodes including (Fig. 2: GL1a, GL2a, GL1b, GL2b)
a first gate electrode and a second gate electrode being apart in a first direction (Fig. 2: GL1a and GL2a are apart in the X-direction), and
a third gate electrode and a fourth gate electrode being apart in the first direction (Fig. 2: GL1b and GL2b are apart in the X-direction),
wherein the second gate electrode and the third gate electrode are configured to receive a first control signal (Fig. 2: GL2a and GL1b; ¶0030: A first control signal A may be applied to the second gate pattern GL1b and the third gate pattern GL2a through the second and third gate contacts CB1b and CB2a.), and
the first gate electrode and the fourth gate electrode are configured receive a second control signal (Fig. 2: GL1a and GL2b; ¶0030: A second control signal B may be applied to the first gate pattern GL1a and the fourth gate pattern GL2b through the first and fourth gate contacts CB1a and CB2b.);
a plurality of drain regions comprising (Fig. 1: output node ND; ¶0007: a plurality of source/drain regions spaced apart from each other in the first direction on the first and second active regions)
a first drain region between the first gate electrode and the second gate electrode (Fig. 1: drain region ND between first and second gate electrodes of PM1 and NM1; ¶0022: The first PMOS transistor PM1 may have a source connected to a first voltage terminal V1, a gate for receiving a first control signal A, and a drain connected to an output node ND. The first NMOS transistor may have a drain connected to an output node ND, a gate for receiving a second control signal B), and
a second drain region between the third gate electrode and the fourth gate electrode (Fig. 1: drain region ND between third and fourth gate electrodes of PM2 and NM2; ¶0022: The second PMOS transistor may have a source connected to a third voltage terminal V3, a gate for receiving the second control signal B, and a drain connected to the output node ND. The second NMOS transistor NM2 may have a drain connected to the output node ND, a gate for receiving the first control signal A, and a source connected to a fourth voltage terminal V4.),
wherein the first drain region and the second drain region are configured to be electrically connected to each other (Fig. 1: drain region ND; ¶0077: The common contact line CAO may be disposed on the source/drain region S/D of the plurality of source/drain regions S/D disposed among the first to fourth gate patterns GL1a, GL1b, GL2a, and GL2b. The common contact line CAO may extend in the second direction Y, and may overlap the first active region AR1, the second active region AR2, and the isolation region IR.);
a front-side wiring layer disposed above the plurality of gate electrodes in a vertical direction and connected to at least one of the plurality of drain regions and the plurality of gate electrodes (Fig. 2: first and second wiring structures DS1 and DS2 disposed above the gate electrodes in a vertical direction-Z; Figs. 5A and 5B show front side wiring layers disposed above gate electrodes Fig. 6 shows front side wiring layers above gate electrodes which contact drain regions; ¶0076: an active contact CA may penetrate the lowermost interlayer insulating film toward the source/drain region S/D; ¶0077: The common contact line CAO may be disposed on the source/drain region S/D of the plurality of source/drain regions S/D disposed among the first to fourth gate patterns GL1a, GL1b, GL2a, and GL2b.); and
However, Jeong does not disclose a backside wiring layer disposed under the plurality of gate electrodes in the vertical direction and connected to at least another one of the plurality of drain regions and the plurality of gate electrodes.
In a similar field of endeavor, Miao discloses a backside wiring layer disposed under the plurality of gate electrodes in the vertical direction and connected to at least another one of the plurality of drain regions and the plurality of gate electrodes (Fig. 43 shows backside power routing 3440A/B disposed underneath a plurality of gate electrodes 3414, 3424 in a vertical direction and connected to S/D regions on said gate electrodes.; 0063: the connections and routing for power may be provided in the backside layers of the device. As used herein, the term “backside” refers to areas in a device that are vertically below an active layer of the device).
Therefore, it would have been obvious to a person having ordinary skill in the art before the effective filing date to have modified the structure disclosed by Jeong to include a backside wiring layer as disclosed by Miao in order to provide technical and space saving advantages for cell layouts implementing stacked transistors or vertical transistors (See Miao, ¶0064).
Re: Claim 2, the combination of Jeong and Miao discloses the integrated circuit of claim 1.
Jeong also discloses further comprising a first active region and a second active region (Fig. 2: AR1 and AR2), each of which extends in the first direction and is apart in a second direction perpendicular to the first direction (Fig. 2: AR1 and AR2 extend in the X-direction and are separated/apart by an isolation region (IR) along a perpendicular direction-Y),
wherein each of the first gate electrode and the second gate electrode extends in the second direction above the first active region (Fig. 2: GL1a and GL2a have a gate structure which extends in the Y-direction, i.e., second direction above active region AR1), and
each of the third gate electrode and the fourth gate electrode extends in the second direction above the second active region (Fig. 2: GL1b and GL2b have a gate structure which extends in the Y-direction, i.e., second direction above active region AR2).
Re: Claim 3, the combination of Jeong and Miao discloses the integrated circuit of claim 1.
Miao also discloses further comprising a backside contact connected to the first drain region and the second drain region and extending in a second direction perpendicular to the first direction (Fig. 43: Backside Power Routing 3440A, is connected to first and second S/D regions 3412, 3412’ using vias and contacts), wherein the first drain region and the second drain region are connected to the backside wiring layer through the backside contact (Fig. 43: Contact 3419, 3419’; Note 3419’ contact label is hidden but follows naming/numbering convention as contacts 3429 and 3429’.).
Therefore, it would have been obvious to a person having ordinary skill in the art before the effective filing date to have modified the structure disclosed by Jeong to include a backside wiring layer as disclosed by Miao in order to provide technical and space saving advantages for cell layouts implementing stacked transistors or vertical transistors (See Miao, ¶0064).
Re: Claim 4, the combination of Jeong and Miao discloses the integrated circuit of claim 3.
Jeong also discloses further comprising contacts respectively disposed on the plurality of gate electrodes (Fig. 2: CB1a/b, CB2a/b contacts disposed on gate electrodes GL1a/b and GL2a/b), wherein the front-side wiring layer comprises front-side wiring patterns respectively disposed on the contacts (Fig. 2: first and second wiring structures DS1/DS2 disposed on said contacts), and at least one of the plurality of gate electrodes is connected to a corresponding front-side wiring pattern through a corresponding one of the contacts (Fig. 2: DS1/DS2 connected to contacts CB1a/b, CB2a/b disposed on gate electrodes GL1a/b and GL2a/b).
Re: Claim 5, the combination of Jeong and Miao discloses the integrated circuit of claim 3.
Jeong also discloses further comprising
a first contact disposed on the first gate electrode (Fig. 2: CB1a disposed on GL1a),
a second contact disposed on the second gate electrode (Fig. 2: CB2a disposed on GL2a),
a third contact disposed on the third gate electrode (Fig. 2: CB1b disposed on GL1b), and a fourth contact disposed on the fourth gate electrode (Fig. 2: CB2b disposed on GL2b),
wherein the front-side wiring layer includes a first front-side wiring pattern disposed on the first contact (Fig. 2: DS1 wiring pattern disposed on contact CB1a via M11, V1, M21, M31),
a second front-side wiring pattern disposed on the second contact (Fig. 2: DS2 wiring pattern disposed on contact CB2a via M13, V1, M23, V2, M32),
a third front-side wiring pattern disposed on the third contact (Fig. 2: DS2 wiring pattern disposed on contact CB1b via M14, V1, M24, V2, M32), and
a fourth front-side wiring pattern disposed on the fourth contact (Fig. 2: DS1 wiring pattern disposed on contact CB2b via M12, M22, M31), and
the first gate electrode is connected to the first front-side wiring pattern through the first contact (Fig. 2: GL1a connected to DS1 wiring pattern through CB1a),
the second gate electrode is connected to the second front-side wiring pattern through the second contact (Fig. 2: GL2a connected to DS2 wiring pattern through CB2a),
the third gate electrode is connected to the third front-side wiring pattern through the third contact (Fig. 2: GL1b connected to DS2 wiring pattern through CB1b), and
the fourth gate electrode is connected to the fourth front-side wiring pattern through the fourth contact (Fig. 2: GL2b connected to DS1 wiring pattern through CB2b).
Re: Claim 11, Jeong discloses an integrated circuit comprising (See Figs. 2 and 6):
a source region and a drain region being apart in a first direction (Fig. 6: S/D regions apart in X-direction);
a first gate electrode extending in a second direction perpendicular to the first direction, between the source region and the drain region (Fig. 2: GL1a extends in Y-direction; Fig. 6: S/D regions with gate electrodes CA);
However, Jeong does not disclose first backside contacts disposed under the source region and the drain region in a vertical direction and respectively connected to the source region and the drain region; and a backside wiring layer connected to the first backside contacts, wherein the source region and the drain region are configured to receive a same voltage from the backside wiring layer through the first backside contacts.
In a similar field of endeavor, Miao discloses first backside contacts disposed under the source region and the drain region in a vertical direction and respectively connected to the source region and the drain region (Fig. 43: Backside Power Routing 3440A/B disposed under S/D regions 3422, 3422’, 3412, 3412’ in a vertical direction and connected to said S/D regions via contacts 3429, 3429’, 3419, 3419’); and
a backside wiring layer connected to the first backside contacts (Fig. 43: Backside Power Routing 3440A/B connected via contacts 3429, 3429’, 3419, 3419’), wherein the source region and the drain region are configured to receive a same voltage from the backside wiring layer through the first backside contacts (Fig. 43: Fig. 43: Backside Power Routing 3440A/B connected to S/D regions via contacts 3429, 3429’, 3419, 3419’; ¶0081: Control signal tracks may provide input or output signal connections to transistor components in cell 100 while power signal tracks may provide power routing to/from Vdd (e.g., the supply voltage) and Vss (e.g., ground) as well as other contemplated power supply connections.).
Therefore, it would have been obvious to a person having ordinary skill in the art before the effective filing date to have modified the structure disclosed by Jeong to include a backside wiring layer as disclosed by Miao in order to provide technical and space saving advantages for cell layouts implementing stacked transistors or vertical transistors (See Miao, ¶0064).
Re: Claim 12, the combination of Jeong and Miao discloses the integrated circuit of claim 11.
Miao further discloses wherein the backside wiring layer extends in the first direction (Fig. 43: Backside Power Routing 3440A/B extends in a first direction from Via 3610B to Contact Via 3429’).
Therefore, it would have been obvious to a person having ordinary skill in the art before the effective filing date to have modified the structure disclosed by Jeong to include a backside wiring layer as disclosed by Miao in order to provide technical and space saving advantages for cell layouts implementing stacked transistors or vertical transistors (See Miao, ¶0064).
Re: Claim 13, the combination of Jeong and Miao discloses the integrated circuit of claim 11.
Miao also discloses further comprising backside vias respectively connected to the first backside contacts (Fig. 43: Fig. 43: Backside Power Routing 3440A/B connected to S/D regions via contacts 3429, 3429’, 3419, 3419’), wherein the source region and the drain region are configured to receive the same voltage from the backside wiring layer through the first backside contacts and the backside vias (Fig. 43: S/D 3422 receives voltage through contact 3429 and Via 3610B from Backside Power Routing 3440B; ¶0081: …power signal tracks may provide power routing to/from Vdd (e.g., the supply voltage) and Vss (e.g., ground) as well as other contemplated power supply connections.).
Therefore, it would have been obvious to a person having ordinary skill in the art before the effective filing date to have modified the structure disclosed by Jeong to include a backside wiring layer as disclosed by Miao in order to provide technical and space saving advantages for cell layouts implementing stacked transistors or vertical transistors (See Miao, ¶0064).
Re: Claim 16, the combination of Jeong and Miao discloses the integrated circuit of claim 11.
Miao also discloses further comprising a backside via connected to the first backside contacts and extending in the first direction (See Fig. 43: Via 3610B, Contact 3429 and Backside Power Routing 3440B extends in a first direction towards Contact Via 3429’),
wherein the source region and the drain region are configured to receive a same voltage from the backside wiring layer through the first backside contacts and the backside via (Fig. 43: S/D 3422 receives voltage through contact 3429 and Via 3610B from Backside Power Routing 3440B; ¶0081: …power signal tracks may provide power routing to/from Vdd (e.g., the supply voltage) and Vss (e.g., ground) as well as other contemplated power supply connections.).
Therefore, it would have been obvious to a person having ordinary skill in the art before the effective filing date to have modified the structure disclosed by Jeong to include a backside wiring layer as disclosed by Miao in order to provide technical and space saving advantages for cell layouts implementing stacked transistors or vertical transistors (See Miao, ¶0064).
Re: Claim 17, the combination of Jeong and Miao discloses the integrated circuit of claim 11.
Jeong also discloses further comprising:
a second gate electrode apart from the first gate electrode (See Fig. 2: GL1a, GL2a, GL1b, and GL2b are spaced apart; Fig. 6 shows active contacts CA spaced apart; ¶0076: an active contact CA may penetrate the lowermost interlayer insulating film toward the source/drain region S/D); and
a front-side wiring layer disposed above the second gate electrode in the vertical direction (Fig. 2: front side wiring layers DS1 and DS2 disposed above GL1a, GL2a, GL1b, and GL2b).
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure:
XIE et al. (US 20230207553 A1) – See Figs. 1A and 1B
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/WILLIAM ADROVEL/Examiner, Art Unit 2898
/Leonard Chang/Supervisory Patent Examiner, Art Unit 2898
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