DETAILED ACTION
Election/Restrictions
Applicant’s election without traverse of claims 1-10 in the reply filed on 04/01/2026 is acknowledged.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-8 are rejected under 35 U.S.C. 103 as being unpatentable over PARK et al. (US 20150028450 A1), hereinafter “Park,” in view of LEHR et al. (US 20070001203 A1), hereinafter “Lehr.”
RE: Claim 1, Park discloses a integrated circuit comprising (See Fig. 10M):
a semiconductor substrate having a first top surface (Fig. 10M: substrate 402 has a first top surface which intersects trench capacitors 460DC);
a first dielectric layer located over the first top surface and having a second top surface (Fig. 10M: interlayer insulating layer 414, i.e., first dielectric layer, located over the first top surface and has a second top surface where trench capacitors extend to);
a trench extending from the second top surface through the first dielectric layer and into the substrate (Fig. 10M: trench capacitors 460DC extend from a second top surface through the insulation layer 414 and into substrate 402);
a conductive trench electrode within the trench (Fig. 10M: electrode 452B; ¶0181: Each of the decoupling capacitors 460DC includes a first electrode 444B that is another part of the first conductive layer 444, a second insulating thin film 446B that is another part of the insulating thin film 446, and a second electrode 452B that is another part of the second conductive layer 452.); and
a dielectric … between the trench electrode and the semiconductor substrate (Fig. 1: insulating film 76; Fig. 10M: insulating thin film 446B, i.e., dielectric liner, between electrode 452B and substrate 402; ¶0075: the second insulating thin film 76 of each of the decoupling capacitors 70A, 70B, and 70C may include an oxide film, a nitride film, an insulating metal oxide film, a high dielectric film, a polymer film, or combinations thereof.).
Park discloses a dielectric as claimed and taught above. Furthermore, Park discloses a structure 460 in Fig. 10M which has a dielectric liner 440. However, for the sake of compact prosecution a reference will be used to teach a dielectric liner around the trench capacitors, Park does not specifically disclose a dielectric liner for the trench capacitors 460DC.
In a similar field of endeavor, Lehr discloses a dielectric liner (Fig. 2C: dielectric layer 242; Fig. 3e: dielectric layer 342, i.e., dielectric liner; ¶0031: dielectric layer 242… a high-k material may be used).
Therefore, it would have been obvious to a person having ordinary skill in the art before the effective filing date of the current application to have modified the structure disclosed in Park to include a dielectric liner as disclosed in Lehr in order to electrically and physically isolates the electrodes (See Lehr, ¶0031).
RE: Claim 2, the combination of Park and Lehr discloses the integrated circuit of claim 1.
Park further discloses wherein the dielectric liner includes a high-K dielectric (¶0076: the second insulating thin film 76 may be formed as high dielectric layers having a dielectric constant higher than that of a silicon oxide layer. For example, the first insulating thin film 36 and the second insulating thin film 76 may have a dielectric constant in the range of between about 10 to about 25.).
RE: Claim 3, the combination of Park and Lehr discloses the integrated circuit of claim 2.
Park further discloses wherein the high-K dielectric is selected from the group consisting of zirconium oxide, hafnium oxide, aluminum oxide, hafnium oxide, titanium oxide, tantalum pentoxide, lanthanum oxide, barium oxide, scandium oxide, yttrium oxide, lutetium oxide, and niobium pentoxide (¶0076: the second insulating thin film 76 may be formed of at least one material selected from the group including hafnium oxide… Zirconium oxide).
RE: Claim 4, the combination of Park and Lehr discloses the integrated circuit of claim 1.
Park further discloses wherein the first dielectric layer covers a transistor gate electrode (Fig. 10M: device 412 is located within insulating layer 414; ¶0149: The FEOL structure 410 may include a plurality of various types of individual devices 412 and an interlayer insulating layer 414. The individual devices 412 may include one or more of various microelectric devices, for example, a metal-oxide-semiconductor field effect transistor (MOSFET)).
RE: Claim 5, the combination of Park and Lehr discloses the integrated circuit of claim 4.
Park further discloses wherein a top surface of the gate electrode extends above the top surface of the substrate by a first distance (Fig. 10M: device 412 has a top surface which extends above the top surface of substrate 402 by a first distance), and
a top surface of the trench electrode extends above the substrate top surface by a second greater distance (Fig. 10M: trench capacitor 450 has a top surface which extends above the top surface of substrate 402 by a second greater distance).
RE: Claim 6, the combination of Park and Lehr discloses the integrated circuit of claim 1.
Park further discloses wherein a second dielectric layer extends between the second top surface and an interconnect layer (Fig. 10M: metal interlayer insulating layer structure 468, i.e., second dielectric layer, which extends between the second top surface and an interconnect layer).
RE: Claim 7, the combination of Park and Lehr discloses the integrated circuit of claim 1.
Park also discloses wherein the dielectric liner is at least 200 nm thick (Fig. 10M: TSV structure 460 has a dielectric liner 440; ¶0157: The via insulating layer 440 may be formed to have a thickness ranging between about 1500 to about 2500 Å, i.e., between 150 nm to 250 nm; Furthermore, Lehr also discloses a dielectric liner 342 in Fig 3e.).
RE: Claim 8, the combination of Park and Lehr discloses the integrated circuit of claim 1.
Park also discloses further comprising a first contact plug having a first length from the trench electrode to an interconnect metallization layer (Fig. 10M: contact plug 474B, i.e., first contact plug, from 460DC to multilayer wiring structure, i.e., interconnect metallization layer), and
However, Park does not clearly show a second contact plug having a greater second length from the substrate top surface to the interconnect metallization layer.
In a similar field of endeavor, Lehr discloses a second contact plug having a greater second length from the substrate top surface to the interconnect metallization layer (Fig. 2C shows a contact plug 244, i.e., second contact plug, which in this embodiment is the same length as the electrodes for the trench capacitors 241. However, Fig. 3e shows another embodiment wherein the tops of the trenches are higher than a transistor 350 instead of being flush with the surface. In this embodiment the electrodes shown in Fig. 2C would have a shorter length than the second contact plug 244.).
Therefore, it would have been obvious to a person having ordinary skill in the art before the effective filing date of the current application to have included modifications as disclosed in Lehr because by providing a three-dimensional configuration, the "two-dimensional consumption" of precious chip area may be reduced for a given target capacitance, or the decoupling capacitance within a specified die region may be significantly increased without requiring additional die area. (See Lehr, ¶0015).
Claims 9 and 10 are rejected under 35 U.S.C. 103 as being unpatentable over PARK et al. (US 20150028450 A1) in view of LEHR et al. (US 20070001203 A1) and HU et al. (US 20180130869 A1), hereinafter “Hu.”
RE: Claim 9, the combination of Park and Lehr discloses the integrated circuit of claim 1.
Park discloses wherein the conductive trench electrode is one of an array of conductive trenches forming a trench capacitor… (Fig. 10M: array of trench capacitors 460DC).
However, the combination of Park, Lehr, and Hu does not expressly disclose having a capacitance density of at least 50 fF/μm2.
Park and Lehr together disclose the basic structure of an array of conductive trench electrodes formed in a semiconductor substrate and isolated by a dielectric liner, integrated with transistors for decoupling applications. Hu expressly teaches that such modular deep-trench capacitors can achieve a trench capacitor density “as much as ten times higher than a known TiN capacitor, e.g., 15 μF/μm2” (Hu, ¶0042).
Because capacitance density is a result-effective variable determined by well-known, optimizable parameters (trench depth/aspect ratio, dielectric constant and thickness, and array packing density), a person having ordinary skill in the art would have found it routine to adjust these parameters within the combined teachings of Park, Lehr, and Hu so as to reach or exceed the “having a capacitance density of at least 50 fF/μm2” threshold while preserving process compatibility and obtaining the predictable benefit of higher on-chip capacitance in a compact area ("[W]here the general conditions of a claim are disclosed in the prior art, it is not inventive to discover the optimum or workable ranges by routine experimentation." In re Aller, 220 F.2d 454, 456, 105 USPQ 233, 235 (CCPA 1955)).
RE: Claim 10 the combination of Park and Lehr discloses the integrated circuit of claim 1.
However, the combination does not disclose wherein the dielectric liner includes alternating layers of different dielectric materials.
In a similar field of endeavor, Hu discloses wherein the dielectric liner includes alternating layers of different dielectric materials (See Fig. 2F; ¶0031: Step 107 comprises forming at least one dielectric layer on a surface of the DTs. FIG. 2F is a cross-sectional depiction showing an in-process integrated trench capacitor after forming dielectric layers which can comprise in one embodiment a silicon oxynitride layer 216 on a silicon nitride layer 215 on a silicon oxide layer 214 on sidewall surfaces of the DTs 212.).
Therefore, it would have been obvious to a person having ordinary skill in the art before the effective filing date of the current application in order to create a trench capacitor with a much higher density than a TiN capacitor (See Hu, ¶0042).
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure:
ANDO et al. (US 9911597 B2) – Fig. 17 shows a structure relevant to the current claims.
CHENG et al. (US 20200066922 A1) – Fig. 4 shows a structure relevant to the current claims.
CHEN et al. (US 20180151474 A1) – Fig. 5F shows a structure relevant to the current claims.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to WILLIAM ADROVEL whose telephone number is (571)272-3048. The examiner can normally be reached 7:30 AM - 5:00 PM.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, LEONARD CHANG can be reached at (571) 270-3691. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/WILLIAM ADROVEL/ Examiner, Art Unit 2898
/Leonard Chang/ Supervisory Patent Examiner, Art Unit 2898
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