DETAILED ACTION
This Action is responsive to the Amendment filed on 11/12/2025.
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
Election/Restrictions
Applicant’s election without traverse of Species 4, reading on, e.g., FIG. 6B and FIG. 8, in the reply filed on 08/11/2025 is acknowledged and entered into the record.
Claims 1-9 and 15, 18-19, 24-30 are withdrawn from further consideration pursuant to 37 CFR 1.142(b) as being drawn to a nonelected Species 1-3 and Species 5-7, there being no allowable generic or linking claim.
In addition to the withdrawn claims drawn to non-elected Species cited above, the Examiner has identified an additional claim to non-elected Species. Specifically, Claim 17 is also drawn to non-elected Species, and is hereby withdrawn.
For example, Claim 17 recites the limitation: a protective layer 522 disposed on the semiconductor chip 310, which reads on FIG. 5A. Since a “glue layer” is recited in Claim 16, the “protective layer” of Claim 17 appears to identify a different layer from the glue layer 320, FIG. 6B, FIG. 8 disposed on the semiconductor chip 310, FIG. 6B, FIG. 8. The elected Species does not have the recited feature.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim 16 is rejected under 35 U.S.C. 102(a)(1) as being anticipated by Liang (US 2020/0028032).
Regarding claim 16, Liang (see, e.g., FIG. 11) discloses a package structure comprising:
a semiconductor chip 22 comprising a first surface e.g., bottom surface of 22, a second surface 221 opposing to the first surface e.g., bottom surface of 22, a side surface 222 between the first surface e.g., bottom surface of 22 and the second surface 221, a first conducting structure e.g., left pad beneath 22 and a second conducting structure e.g., right pad beneath 22, wherein the first conducting structure e.g., left pad beneath 22 and the second conducting structure e.g., right pad beneath 22 are located on the first surface e.g., bottom surface of 22 of the semiconductor chip 22 (Para 0028, Para 0029);
a glue layer 5, 23 disposed directly surrounding the side surface 222 of the semiconductor chip 22 (Para 0026, Para 0029, Para 0043, Para 0045-Para 0048);
a support 3 disposed on the glue layer 5, 23 (Para 0026, Para 0036); and
an optical component 6 disposed on the support 3 (Para 0026).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim 20 is rejected under 35 U.S.C. 103 as being unpatentable over Liang (US 2020/0028032), in view of Adachi (US 2016/0336716).
Regarding claim 20, although Liang shows substantial features of the claimed invention, Liang fails to expressly teach that the optical component includes a micro lens array (MLA) or a diffraction optical element (DOE).
Adachi (see, e.g., FIG. 6) teaches package structure of claim 16, wherein the optical component 20 includes a micro lens array (MLA) 22 or a diffraction optical element (DOE) for the purpose of condensing the light emitted by the light emitting chip (Para 0064, Para 0129).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the optical component of Liang to include a micro lens array (MLA) as described by Adachi for the purpose of condensing the light emitted by the light emitting chip (Para 0129).
Claim 21 is rejected under 35 U.S.C. 103 as being unpatentable over Liang (US 2020/0028032), in view of Park (KR 2019 0084807 A).
Regarding claim 21, although Liang shows substantial features of the claimed invention, Liang fails to expressly teach a patterned layer disposed on the second surface of the semiconductor chip.
Park (see, e.g., FIG. 9) teaches the package structure of claim 16, further comprising a patterned layer 310 disposed on the second surface e.g., top surface of 310 of the semiconductor chip 120 for the purpose of condensing the light emitted through the upper surface of the of the light emitting chip (Para 0080, Para 0081).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to include patterned layer as described by Park to the second surface of the semiconductor chip of Liang for the purpose of condensing the light emitted through the upper surface of the of the light emitting chip (Para 0080, Para 0081).
Claim 22 is rejected under 35 U.S.C. 103 as being unpatentable over Liang (US 2020/0028032), in view of Organesian (US 2021/0172581).
Regarding claim 22, although Liang shows substantial features of the claimed invention, Liang fails to expressly teach that the optical component includes a diffraction patterned structure.
Organesian (see, e.g., FIG. 7C, FIG. 7D, FIG. 7F, FIG. 8B) teaches the package structure of claim 16, wherein the optical component 116 includes a diffraction patterned structure 96 for the purpose of providing the desired diffraction of the output for even and non-even light distribution as needed (Para 0030-Para 0034).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the optical component in the device of Liang for the optical component that includes a diffraction pattern as described by Organesian for the purpose of providing the desired diffraction of the output for even and non-even light distribution as needed (Para 0034).
Claims 10-11 are rejected under 35 U.S.C. 103 as being unpatentable over Watanabe (US 2015/0263239), in view of Chu (US 2020/0227597).
Regarding claim 10, Watanabe (see, e.g., FIG. 11) discloses semiconductor laser structure comprising:
a chip 1 comprising a first surface e.g., bottom surface of 1, a second surface e.g., top surface of 1 opposing to the first surface e.g., bottom surface of 1, a side surface e.g., side surface of 1 between the first surface e.g., bottom surface of 1 and the second surface e.g., top surface of 1, a first conducting structure 6a and a second conducting structure 6b, wherein the first conducting structure 6a and the second conducting structure 6b are located on the first surface e.g., bottom surface of 1 of the chip 1 (Para 0045, Para 0059);
a protective layer 2, 3 disposed on the second surface e.g., top surface of 1 of the chip 1 (Para 0045, Para 0046, Para 0048, Para 0059); and
an optical component 33 disposed on the protective layer 2, 3 (Para 0060),
Although Watanabe shows substantial features of the claimed invention, Watanabe fails to expressly teach a vertical cavity surface emitting laser chip.
Chu (see, e.g., FIG. 3) teaches a vertical cavity surface emitting laser chip 140 for the purpose of utilizing a light emitting device that has low energy consumption, long life, small size, and fast switching speeds (Para 0003, Para 0072).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the LED chip of Watanabe for the vertical cavity surface emitting laser as described by Chu for the purpose of utilizing a light emitting device that has low energy consumption, long life, small size, and fast switching speeds (Para 0003).
Regarding claim 11, Watanabe (see, e.g., FIG. 11) teaches the semiconductor laser structure of claim 10, further comprising a support 9 disposed on a perimeter of the protective layer 2, 3 (Para 0046).
Claim 12 is rejected under 35 U.S.C. 103 as being unpatentable over Watanabe (US 2015/0263239), in view of Chu (US 2020/0227597), and further in view of Adachi (US 2016/0336716).
Regarding claim 12, although Watanbe/Chu show substantial features of the claimed invention, Watanabe/Chu fail to expressly teach that the optical component includes a micro lens array (MLA) or a diffraction optical element (DOE).
Adachi (see, e.g., FIG. 6) teaches the semiconductor laser structure of claim 10, wherein the optical component 20 includes a micro lens array (MLA) 22 or a diffraction optical element (DOE) for the purpose of increasing the output of the laser device (Para 0058, Para 0064, Para 0068, Para 0091).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the optical component of Watanabe/Chu for the optical component that includes a micro lens array (MLA) as described by Adachi for the purpose of increasing the output of the laser device (Para 0091).
Claim 13 is rejected under 35 U.S.C. 103 as being unpatentable over Watanabe (US 2015/0263239), in view of Chu (US 2020/0227597), and further in view of Organesian (US 2021/0172581).
Regarding claim 13, although Watanbe/Chu show substantial features of the claimed invention, Watanabe/Chu fail to expressly teach that the optical component includes a diffraction patterned structure.
Organesian (see, e.g., FIG. 7C, FIG. 7D, FIG. 7F, FIG. 8B) teaches semiconductor laser structure of claim 10, wherein the optical component 116 includes a diffraction patterned structure 96 for the purpose of providing the desired diffraction of the output for even and non-even light distribution as needed (Para 0030-Para 0034).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the optical component in the device of Watanabe/Chu for the optical component that includes a diffraction pattern as described by Organesian for the purpose of providing the desired diffraction of the output for even and non-even light distribution as needed (Para 0034).
Allowable Subject Matter
Claims 14 and 23 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Response to Arguments
Applicant's arguments filed 11/12/2025 have been fully considered but they are not persuasive.
Applicant argues:
Applicant argues that Watanabe Reference discloses a light emitting apparatus with an LED device, but Watanabe's architecture is fundamentally designed for an omnidirectional LED source, not a vertical cavity surface emitting laser (VCSEL) chip as claimed.
Examiner responds:
Examiner respectfully disagrees. Devices with vertical cavity emitting laser (VCSEL) chip and reflective sidewalls are manufactured along with omnidirectional LED source with reflective sidewalls. For example, Lu (US 2019/0198549; see, e.g., FIG. 5) discloses a light emitting device that includes a VCSEL chip (includes substrate 10, contact 12) and reflective layers 50, 52 disposed on the sidewalls of the VCSEL chip (Para 0011, Para 0012, Para 0036). Therefore, Watanabe’s device can be modified to include a VCSEL chip.
Applicant argues:
Applicant argues that Watanabe fails to teach the claimed features "a protective layer disposed on the second surface of the VCSEL chip" of claim 10. The Examiner alleges that the phosphor layer 2 and the reflective resin 3 in Watanabe teach the claimed features. However, referring to the disclosure in Watanabe, Watanabe's architecture is fundamentally designed for an omnidirectional LED source because its LED device 1 is flip-chip mounted at the bottom of a cavity, and its side-emitted light is redirected upward by the reflective resin 3 (see Watanabe, [0045]-[0046], Figs. 1, 2). The phosphor layer 2 and resin 3, taught in Watanabe, are arranged to convert and redirect the omnidirectional light from the LED device 1 rather than to protect the LED device 1. Therefore, Watanabe's phosphor layer 2 and resin 3 cannot be reasonably interpreted to be a "protective layer" as claimed.
Examiner responds:
The Examiner respectfully disagrees. Protect is defined as to cover or shield from exposure, and so a protective layer covers or shields something from exposure. Watanabe Reference teaches that the phosphor layer 2 is bonded to the top surface of LED device 1, and that side surface of the LED device 1 and the side surface of the phosphor layer 2 are sealed by the reflective resin 3. The phosphor layer 2 and the reflective resin 3, in addition to wavelength conversion and reflectance, protect (i.e., cover or shield) the LED device 1 from exposure because the phosphor layer 2 and the reflective resin 3 encapsulate or seal the LED device 1.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to ANTONIO CRITE whose telephone number is (571) 270-5267. The examiner can normally be reached Monday - Friday, 10:00 am - 6:30 pm.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Kretelia Graham can be reached at (571) 272-5055. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/ANTONIO B CRITE/Primary Examiner, Art Unit 2817