DETAILED ACTION
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
In response to a Restriction Requirement filed on 03/05/2026, the Applicant elected without traverse Group I (claims 1-14) in a reply filed on 04/10/2026. Claims 15-25 are withdrawn from further consideration pursuant to 37 CFR 1.142(b) as being drawn to a nonelected Group II, there being no allowable generic or linking claim.
Currently, claims 1-14 are examined as below.
Priority
Receipt is acknowledged of certified copies of papers required by 37 CFR 1.55.
Information Disclosure Statement
Acknowledgment is made of applicant's Information Disclosure Statement (IDS) filed on 12/27/2023. The IDS has been considered.
Specification
The title of the invention is not descriptive. A new title is required that is clearly indicative of the invention to which the claims are directed.
The following title is suggested:
(Marked-Up Version) Semiconductor Device Having Stable Structure, Improved Characteristic and Integration Degree
(Clean Version) Semiconductor Device Having Stable Structure, Improved Characteristic and Integration Degree
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claims 1-6 and 8-13 are rejected under 35 U.S.C. 102(a)(2) as being anticipated by US 2024/0194266 A1 to Kim et al. (“Kim”).
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Regarding independent claim 1, Kim in Fig. 2 teaches a semiconductor device (Fig. 2 & ¶ 39, semiconductor device) comprising:
a first group of stacked first gate lines 130/LA2 (Fig. 2 & ¶ 52, gate electrodes 130 of second stack structures LA2), and a second group of stacked second gate lines 130/LA1 (Fig. 2 & ¶ 52, gate electrodes 130 of first stack structures LA1) overlapping with the first group of the first stacked lines 130/LA2 (Fig. 2), the first and second groups 130/LA2, 130/LA1 being spaced apart from each other (Fig. 2 & ¶ 49, gate electrodes 130 of stack LA2 is spaced apart from gate electrodes 130 of stack LA1 by an interlayer insulating layer 120 in between), wherein the first gate lines 130 and the second gate lines 130 alternate with insulation layers 120 (Fig. 2 & ¶ 49, interlayer insulating layers 120);
a channel structure CH (Fig. 2 & ¶ 49, channel structure CH) extending through the first gate lines 130 and the second gate lines 130;
first contact plugs 150/LA2 (Fig. 2, ¶ 30 & ¶ 52, contact plugs 150 in the second stack structure LA2) extending through the first gate lines 130/LA2 and respectively connected to front surfaces (Fig. 2, lower surfaces) of the first gate lines 130/LA2 (Fig. 2, ¶ 30 & ¶ 54); and
second contact plugs 150/LA1 (Fig. 2, ¶ 30 & ¶ 52, contact plugs 150 in the first stack structure LA1) extending through the second gate lines 130/LA1 and respectively connected to rear surfaces (Fig. 2, upper surfaces) of the second gate lines 130/LA1 (Fig. 2, ¶ 30 & ¶ 54).
Regarding claim 2, Kim in Fig. 2 further teaches the first contact plugs 150/LA2 extend in different depths through the first gate lines 130/LA2 (Fig. 2, the contact plugs 150 in stack LA2 extend through the gate lines 130 in stack LA2, in which the gate lines 130 are in different depths).
Regarding claim 3, Kim in Fig. 2 further teaches the second contact plugs 150/LA1 extend in different depths through the second gate lines 130/LA2 (Fig. 2, the contact plugs 150 in stack LA1 extend through the gate lines 130 in stack LA1, in which the gate lines 130 are in different depths).
Regarding claim 4, Kim in Fig. 2 further teaches a dummy stack DS1, DS2, DS3, DS4 (Fig. 2 & ¶ 32, first dummy structure DS1, second dummy structure DS2, third dummy structure DS3, or fourth dummy structure DS4);
a peripheral circuit S1 (Fig. 2 & ¶ 41, first substrate structure S1 includes a peripheral circuit region); and
a third contact plug 150/DS2, 150/DS4 (Fig. 2, ¶ 30 & ¶ 37, contact plugs 150 in the stack LA2 that extend through the dummy structures DS2, DS4) extending through the dummy stack DS2, DS4 and connecting the second contact plugs 150/LA1 and the peripheral circuit S1 (Fig. 2 & ¶ 42, the contact plugs 150 in stack DS2, DS4 and in stack LA2 connect the contact plugs 150 in the stack LA1 with the circuit contact plugs 270 and the circuit interconnection lines 280 in the peripheral region S1).
Regarding claim 5, Kim in Fig. 2 further teaches a peripheral circuit S1 (Fig. 2 & ¶ 41, first substrate structure S1 includes a peripheral circuit region); and
an interconnection structure 170, 180, 195, 198 (Fig. 2, ¶ 49 & ¶ 74, a collective of cell contact plugs 170, cell interconnection lines 180, second bonding vias 195 and second metal bonding pads 198) connecting the peripheral circuit S1 to the first contact plugs 150/LA2 and the second contact plugs 150/LA1 (¶ 71-¶ 72).
Regarding claim 6, Kim in Fig. 2 further teaches the interconnection structure 170, 180, 195, 198 includes a bonding pad 198 (¶ 74, second metal bonding pad 198).
Regarding claim 8, Kim in Fig. 2 further teaches the first contact plugs 150/LA2 are positioned under the second contact plugs 150/LA1, respectively (Fig. 2).
Regarding claim 9, Kim in Fig. 2 further teaches the first contact plugs 150/LA2 have a taper shape cross-section (Fig. 2) and the second contact plugs 150/LA1 have an inverted taper shape cross-section (see a flipped Fig. 2).
Regarding independent claim 10, Kim in Fig. 2 teaches a semiconductor device (Fig. 2 & ¶ 39, semiconductor device) comprising:
a peripheral circuit S1 (Fig. 2 & ¶ 41, first substrate structure S1 includes a peripheral circuit region);
a gate structure 130 (Fig. 2 & ¶ 30, a collective of gate electrodes 130) including a front surface (Fig. 2, lower surface) facing the peripheral circuit S1;
a first contact plug 150/LA2 (Fig. 2, ¶ 30 & ¶ 52, contact plugs 150 in the second stack structure LA2) extending into the gate structure 130 through the front surface (Fig. 2 lower surface);
a second contact plug 150/LA1 (Fig. 2, ¶ 30 & ¶ 52, contact plugs 150 in the first stack structure LA1) extending into the gate structure 130 through a rear surface (Fig. 2, upper surface of the gate structure 130); and
an interconnection structure 170, 180, 195, 198 (Fig. 2, ¶ 49 & ¶ 74, a collective of cell contact plugs 170, cell interconnection lines 180, second bonding vias 195 and second metal bonding pads 198) connecting the first contact plug 150/LA2 and the second contact plug 150/LA1 to the peripheral circuit S1 (¶ 71-¶ 72).
Regarding claim 11, Kim in Fig. 2 further teaches a dummy stack DS1, DS2, DS3, DS4 (Fig. 2 & ¶ 32, first dummy structure DS1, second dummy structure DS2, third dummy structure DS3, or fourth dummy structure DS4) connected to the gate structure 130 (Fig. 2, the structures 130 in the structure DS1, DS2, DS3, DS4 connect to the gate structures 130 in other regions of the stack LA1, LA2); and
a third contact plug 150/DS2, 150/DS4 (Fig. 2, ¶ 30 & ¶ 37, contact plugs 150 that extend through the dummy structures DS2, DS4 in the stack LA2) extending through the dummy stack DS2, DS4 and connected to the second contact plug 150/LA1 (Fig. 2),
wherein the interconnection structure 170, 180, 195, 198 connects the third contact plug 150/DS2, 150/DS4 (in the stack LA2) and the peripheral circuit S1 (Fig. 2 & ¶ 71-¶ 72).
Regarding claim 12, Kim in Fig. 2 further teaches the interconnection structure 170, 180, 195, 198 includes a bonding pad 198 (¶ 74, second metal bonding pad 198).
Regarding claim 13, Kim in Fig. 2 further teaches a channel structure CH (Fig. 2 & ¶ 49, channel structure CH) extending through the gate structure 130.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention.
Claims 7 and 14 are rejected under 35 U.S.C. 103 as being unpatentable over Kim in view of US 2023/0403854 A1 to Kim et al. (“Kim854”).
Regarding claim 7, Kim does not explicitly disclose Insulating spacers surrounding sidewalls of the first contact plugs and the second contact plugs, respectively.
Kim854 recognizes a need for insulating a conductive contact plug from other components (Fig. 4 & ¶ 88). Kim854 satisfies the need by providing Insulating spacers 153 (Fig. 4 & ¶ 88, first spacer film 153 including an insulating material) surrounding sidewalls of contact plugs 154 (Fig. 4 & ¶ 88, first filling film 154 including a conductive material), respectively.
Before the effective filing date of the claimed invention, it would have been obvious to one of ordinary skill in the art to combine the insulating spacers taught by Kim854 with the first and second conduct plugs taught by Kim, so as to insulate a conductive contact plug from other components (Kim854: Fig. 4 & ¶ 88).
Regarding claim 14, Kim does not explicitly disclose Insulating spacers surrounding sidewalls of the first contact plugs and the second contact plugs, respectively.
Kim854 recognizes a need for insulating a conductive contact plug from other components (Fig. 4 & ¶ 88). Kim854 satisfies the need by providing Insulating spacers 153 (Fig. 4 & ¶ 88, first spacer film 153 including an insulating material) surrounding sidewalls of contact plugs 154 (Fig. 4 & ¶ 88, first filling film 154 including a conductive material), respectively.
Before the effective filing date of the claimed invention, it would have been obvious to one of ordinary skill in the art to combine the insulating spacers taught by Kim854 with the first and second conduct plugs taught by Kim, so as to insulate a conductive contact plug from other components (Kim854: Fig. 4 & ¶ 88).
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
US 2022/0045083 A1 to Sim et al.
US 2022/0392916 A1 to Baek et al.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to MIKKA LIU whose telephone number is (571)272-2568. The examiner can normally be reached on 9AM-5AM EST M-F.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Eliseo Ramos-Feliciano can be reached on 571-272-7925. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/M.L./Examiner, Art Unit 2817
/ELISEO RAMOS FELICIANO/Supervisory Patent Examiner, Art Unit 2817
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