DETAILED ACTION
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
In response to an Office action mailed on 05/21/2026 (“05/21/2026 OA”), the Applicant amended independent claim 1 and 10, canceled claims 15-25 and added new claims 26-29 in a reply filed on 08/21/2026. Applicant’s amendments substantively changed the scope of claims 1 and 10 as well as their respective dependent claims.
Currently, claims 1-14 and 26-29 are examined as below.
Response to Arguments
Applicant’s amendments to the title of the invention have overcome the specification objections as set forth under line item number 1 in the 05/21/2026 OA.
Applicant’s amendments to independent claims 1 and 10 have overcome the prior-art rejections as set forth under line item numbers 2-3 in the 05/21/2026 OA.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1-3, 5-10, 12-14, 26 and 29 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by US 2022/0077126 A1 to Choi et al. (“Choi”).
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Regarding independent claim 1, Choi in Fig. 4 teaches a semiconductor device (Fig. 4 & ¶ 61, semiconductor memory device) comprising:
a first group of stacked first gate lines 20a (¶ 64, first electrode layers 20a), and a second group of stacked second gate lines 20b (¶ 72, second electrode layer 20b) overlapping with the first group of the first stacked first gate lines 20a (Fig. 4), the first and second groups 20a, 20b being spaced apart from each other (Fig. 4, ¶ 44, gate lines 20a and 20b are separated by source plate 10), wherein the first gate lines 20a and the second gate lines 20b alternate with insulation layers 22a, 22b (Fig. 4, ¶ 63, ¶ 72, first interlayer dielectric layers 22a and second interlayer dielectric layers 22b);
a channel structure CHa, CHb (Fig. 4, ¶ 63, ¶ 72, a collective of first vertical channels CHa and second vertical channels CHb) extending through the first gate lines 20a and the second gate lines 20b;
first contact plugs CHa (Fig. 4, ¶ 63, first vertical channels CHa) extending through the first gate lines 20a and respectively connected to front surfaces of the first gate lines 20a (Fig. 4, side surfaces of the channels CHa connect to ends of lower/front surfaces of the gate lines 20a), wherein the first contact plugs CHa are spaced apart from the second gate lines 20b (Fig. 4); and
second contact plugs CHb (Fig. 4, ¶ 72, second vertical channels CHb) extending through the second gate lines 20b and respectively connected to rear surfaces of the second gate lines 20b (Fig. 4, side surfaces of the channel CHb connect to ends of upper/rear surfaces of the gate lines 20b), wherein the second contact plugs CHb are spaced apart from the first gate lines 20a (Fig. 4).
Regarding claim 2, Choi in Fig. 4 further teaches the first contact plugs CHa extend in different depths through the first gate lines 20a (Fig. 4, plugs CHa on the sides have different depths through the gate lines 20a than the plugs CHa in the center).
Regarding claim 3, Choi in Fig. 4 further teaches the second contact plugs 20b extend in different depths through the second gate lines 20b (Fig. 4, plugs CHb on the sides have different depths through the gate lines 30b than the plugs CHb in the center).
Regarding claim 5, Choi in Fig. 4 further teaches a peripheral circuit 120A, 120B (¶ 45, first logic circuit unit 120A; ¶ 78, second logic circuit unit 120B); and
an interconnection structure BL1-BL2, BP1-BP4 (¶ 49-¶ 50, ¶ 70, ¶ 77, ¶ 79-¶ 80, a collective of first bit lines BL1, second bit lines BL2, first bonding pad BP1, second bonding pad BP2, third bonding pad BP3 and fourth bonding pad BP4) connecting the peripheral circuit 120A, 120B to the first contact plugs CHa and the second contact plugs CHb (Fig. 4).
Regarding claim 6, Choi in Fig. 4 further teaches the interconnection structure BL1-BL2, BP1-BP4 includes a bonding pad BP1, BP2, BP3, BP4 (¶ 70, ¶ 77, ¶ 79-¶ 80).
Regarding claim 7, Choi in Fig. 4 further teaches insulating spacers ILD1, ILD2 (Fig. 4, ¶ 70, ¶ 77, dielectric layers ILD1 and ILD surround at least a part of the sidewalls of each of the contact plugs CHa and CHb) surrounding sidewalls of the first contact plug CHa and the second contact plug CHb, respectively.
Regarding claim 8, Choi in Fig. 4 further teaches the first contact plugs 20a are positioned under the second contact plugs 20b, respectively.
Regarding claim 9, Choi in Fig. 4 further teaches the first contact plugs 20a have a taper shape cross-section and the second contact plugs 20b have an inverted taper shape cross-section (Fig. 4).
Regarding independent claim 10, Choi in Fig. 4 teaches a semiconductor device (Fig. 4 & ¶ 61, semiconductor memory device) comprising:
a peripheral circuit 120A, 120B (¶ 45, first logic circuit unit 120A; ¶ 78, second logic circuit unit 120B);
a gate structure 20a, 20b (¶ 64, ¶ 72, a collective of first electrode layers 20a and second electrode layer 20b) including a front surface (Fig. 4, lower surface) facing the peripheral circuit 120A;
a first contact plug CHa (Fig. 4, ¶ 63, first vertical channels CHa) extending into the gate structure 20a, 20b through the front surface;
a second contact plug CHb (Fig. 4, ¶ 72, second vertical channels CHb) extending into the gate structure 20a, 20b through a rear surface (Fig. 4, upper surface); and
an interconnection structure BL1-BL2, BP1-BP4 (¶ 49-¶ 50, ¶ 70, ¶ 77, ¶ 79-¶ 80, a collective of first bit lines BL1, second bit lines BL2, first bonding pad BP1, second bonding pad BP2, third bonding pad BP3 and fourth bonding pad BP4) connecting the first contact plug CHa and the second contact plug CHb to the peripheral circuit 120A, 120B (Fig. 4),
wherein the first contact plug 20a has a tapered shape (Fig. 4) and the second contact plug 20b has an inverted tapered shape (Fig. 4) with respect to the first contact plug 20a.
Regarding claim 12, Choi in Fig. 4 further teaches the interconnection structure BL1-BL2, BP1-BP4 includes a bonding pad BP1, BP2, BP3, BP4 (¶ 70, ¶ 77, ¶ 79-¶ 80).
Regarding claim 13, Choi in Fig. 4 further teaches a channel structure CHa, CHb (¶ 63, ¶ 72, first vertical channels CHa and second vertical channels CHb) extending through the gate structure 20a, 20b.
Regarding claim 14, Choi in Fig. 4 further teaches insulating spacers ILD1, ILD2 (Fig. 4, ¶ 70, ¶ 77, dielectric layers ILD1 and ILD surround at least a part of the sidewalls of each of the contact plugs CHa and CHb) surrounding sidewalls of the first contact plug CHa and the second contact plug CHb, respectively.
Regarding independent claim 26, Choi Fig. 4 teaches a semiconductor device (Fig. 4 & ¶ 61, semiconductor memory device) comprising:
first gate lines 20a (¶ 64, first electrode layers 20a);
second gate lines 20b (¶ 72, second electrode layer 20b) stacked over the first gate lines 20a;
first contact plugs CHa (Fig. 4, ¶ 63, first vertical channels CHa) extending through the first gate lines 20a and respectively connected to the first gate lines 20a (Fig. 4, ¶ 69-¶ 71), wherein the first contact plugs CHa are spaced apart from the second gate lines 20a (Fig. 4); and
second contact plugs CHb (Fig. 4, ¶ 72, second vertical channels CHb) extending through the second gate lines 20b and respectively connected to the second gate lines 20b (¶ 76-¶ 77), wherein the second contact plugs CHb are spaced apart from the first gate lines 20a (Fig. 4).
Regarding claim 29, Choi in Fig. 4 further teaches the second contact plugs CHb have an inverted tapered shape with respect to the first contact plugs CHa (Fig. 4).
Allowable Subject Matter
The following is a statement of reasons for the indication of allowable subject matter:
Claims 4, 11 and 27-28 are objected to as being dependent upon a rejected base claim, but would be allowable if (i) rewritten in independent form to include all of the limitations of the base claim and any intervening claims or (ii) the objected claim and any intervening claims are fully incorporated into the base claim.
Claim 4 would be allowable, because the prior art of record, singularly or in combination, fails to disclose or suggest, in combination with the other claimed elements in claim 4, a dummy stack; a peripheral circuit; and a third contact plug extending through the dummy stack and connecting the second contact plugs and the peripheral circuit.
Claim 11 would be allowable, because the prior art of record, singularly or in combination, fails to disclose or suggest, in combination with the other claimed elements in claim 11, a dummy stack connected to the gate structure; and a third contact plug extending through the dummy stack and connected to the second contact plug, wherein the interconnection structure connects the third contact plug and the peripheral circuit.
Claim 27 would be allowable, because the prior art of record, singularly or in combination, fails to disclose or suggest, in combination with the other claimed elements in claim 27, a peripheral circuit disposed under the first gate lines; a dummy stack disposed over the peripheral circuit; and a third contact plug extending through the dummy stack.
Claim 28 would be allowable, because claim 28 depends from the allowable claim 27.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to MIKKA LIU whose telephone number is (571)272-2568. The examiner can normally be reached on 9AM-5AM EST M-F.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Eliseo Ramos-Feliciano can be reached on 571-272-7925. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/M.L./Examiner, Art Unit 2817
/ELISEO RAMOS FELICIANO/Supervisory Patent Examiner, Art Unit 2817
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