DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Election/Restrictions
Applicant’s election without traverse of Invention I, claims 1-12, 13-16, and 23-27 in the reply filed on 04/13/2026 is acknowledged. Applicant’s election with traverse of Species I, claims 1-16, 23, and 27 is also acknowledged.
Applicant submits that “First, a valid restriction must be based on the Claims and not the Figures. The MPEP is explicit that for a restriction to be proper, the inventions must be "independent or distinct as claimed" (MPEP § 803). the examiner's entire distinctness analysis must hinge on the specific language of the claims and not the figures. Second, … The Examiner provides no evidence of separate status in the art, requirement of a a different field of search, etc. Applicant submits that a search for isolation device would produce results independent of whether a transformer based isolation, or a inductive, capacitive, or optical coupling is used.”. This argument has been considered but is not persuasive.
The species requirement was based on the claimed subject matter and not solely on the figures. Further, Applicant has not persuasively shown that the claimed species would require the same search and examination efforts. As set forth in the restriction requirement, the species are directed to different subject matter and would require different search and examination efforts.
Accordingly, the species restriction is maintained.
Claim 24-26 are withdrawn from consideration as being drawn to nonelected Species II.
Information Disclosure Statement
The information disclosure statement (IDS) filed on 03/19/2025, IDS filed on 07/03/2025, and IDS filed on 04/14/2026 are in compliance with the provisions of 37 CFR 1.97. Accordingly, the IDSs are considered by the examiner.
Specification
The title of the invention is not descriptive. A new title is required that is clearly indicative of the invention to which the claims are directed.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1-4, 6-12, 23, and 27 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Lueders et al. (US 2021/0258045; hereinafter ‘Lueders’).
Regarding claim 1, Lueders teaches an isolation device (900, FIGS. 9-10, [0055]), comprising:
a multi-level substrate (902 including 1000, 1002, and 1004 embedded within 1014, [0056-0057]) having opposing first (a surface portion of 902 associated with IC 910, [0056]; hereinafter ‘902S1’) and second surfaces (a surface portion of 902 associated with IC 920; hereinafter ‘902S2’), the multi-level substrate (902) including:
a first coil (winding 906, [0059, 0064]) in a first layer (1000, [0066]) of the substrate (902), the first coil (906) having first (918-1, [0061]) and second terminals (918-2);
a second coil (winding 908, [0059, 0065]) in a second layer (1004, [0066]) of the substrate (902) that is vertically distanced from the first layer (1004 is vertically distanced from 1000, FIG. 10), the second coil (908) having third (932-1, [0061]) and fourth terminals (932-2); and
a dielectric material (1014, [0036, 0058]) covering the first (906) and second coils (908);
a first semiconductor die (910) coupled to the first surface (902S1) and to the first (918-1) and second terminals (918-2);
a second semiconductor die (920) coupled to the second surface (902S2) and to the third (932-1) and fourth terminals (932-2), the second semiconductor die (920) galvanically isolated from the first semiconductor die (910, wherein a galvanic isolation barrier forms between 920 and 910, [0060]);
conductive terminals (948, [0057]) coupled to the multi-level substrate (902, wherein 948 coupled to 902, [0063]); and
a mold compound (1012, [0056]) covering the multi-level substrate (902), the first (910) and second semiconductor dies (920), and the conductive terminals (948, wherein 1012 covers 902, 910, 920, and 948, [0056]).
Regarding claim 2, Lueders teaches the device of claim 1, wherein the dielectric material comprises a build-up film (1014 comprises Ajinomoto build-up film (ABF), [0036, 0058]).
Regarding claim 3, Lueders teaches the device of claim 1, wherein the conductive terminals are coupled to the second surface (the right-side 948 coupled to 902S2, FIG. 9).
Regarding claim 4, Lueders teaches the device of claim 1, wherein the conductive terminals are coupled to the first surface (the left-side 948 coupled to 902S1, FIG. 9).
Regarding claim 6, Lueders teaches the device of claim 1, wherein no vertical line that is orthogonal to the first and second surfaces extends through both the first and second semiconductor dies (a line orthogonal to 902S1 and 902S2 does not extend through both 910 and 920, since 910 and 920 are laterally separated and are positioned at different vertical levels with respect to 902S1 and 902S2, FIGS. 9 and 10).
Regarding claim 7, Lueders teaches the device of claim 1, wherein the first layer is between the first surface and the second layer (1000 is between 902S1 and 902S2, FIGS. 9-10).
Regarding claim 8, Lueders teaches the device of claim 1, wherein the second layer is between the second surface and the first layer (1004 is between 902S1 and 902S2, FIGS. 9-10).
Regarding claim 9, Lueders teaches the device of claim 1, wherein the dielectric material is a solid dielectric material and not air (1014 comprises Ajinomoto build-up film (ABF), [0036, 0058]).
Regarding claim 10, Lueders teaches the device of claim 1, wherein the first and second coils form a transformer (906 and 908 form a transformer, [0059]).
Regarding claim 11, Lueders teaches the device of claim 1, wherein the first and second semiconductor dies are coupled to the first, second, third, and fourth terminals by solder bumps (910 and 920 are coupled to 918-1, 918-2, 932-1, and 932-2 by solder balls, [0061-0062]).
Regarding claim 12, Lueders teaches the device of claim 1, wherein device sides of the first and second semiconductor dies in which circuitry is formed face the substrate (device sides of 910 and 920 having circuitry formed therein face circuit support structure 902, [0061-0062]).
Regarding claim 23, Lueders teaches an isolation package (900, FIGS. 9-10, [0055]), comprising:
a substrate (902, [0056]) having first (winding 906, [0059, 0064]) and second coupling members (winding 908, [0059, 0065]) and first (a surface portion of 902 associated with IC 910, [0056]; hereinafter ‘902S1’) and second surfaces (a surface portion of 902 associated with IC 920; hereinafter ‘902S2’), the first and second surfaces opposing each other (902S1 and 902S2 opposing each other);
a first semiconductor die (910) coupled to the first surface (902S1) and to the first coupling member (906, wherein 910 coupled to 902S1 and 906);
a second semiconductor die (920) coupled to the second surface (902S2) and to the second coupling member (908, wherein 920 coupled to 902S2 and 908), the second semiconductor die (920) galvanically isolated from the first semiconductor die (910, wherein a galvanic isolation barrier forms between 920 and 910, [0060]);
conductive terminals (948, [0057]) coupled to the substrate (902, wherein 948 coupled to 902, [0063]); and
a mold compound (1012, [0056]) covering the substrate (902), the first (910) and second semiconductor dies (920), and the conductive terminals (948, wherein 1012 covers 902, 910, 920, and 948, [0056]).
Regarding claim 27, Lueders teaches the package of claim 23, wherein the conductive terminals are package leads (948 functions as package leads because it provides electrical connection between IC package 900 and an external circuit support structure, [0063]).
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 5 and 13-16 are rejected under 35 U.S.C. 103 as being unpatentable over Lueders (US 2021/0258045) in view of O’Donnell et al. (US 2016/0109399; hereinafter ‘O’Donnell’).
Regarding claim 5, Lueders teaches the device of claim 1, but does not teach the device wherein a vertical line orthogonal to the first and second surfaces extends through both the first and second semiconductor dies.
O’Donnell teaches a device (1300, FIG. 13, [0113]) wherein a vertical line orthogonal to the first and second surfaces extends through both the first and second semiconductor dies (second semiconductor die 1320 is stacked above first semiconductor die 1310 with first coil 1350.1 and second coil 1350.2 disposed in substrate 1330 between dies 1310 and 1320, a line orthogonal to surface portions associated with the coil structures extending through both dies 1310 and 1320).
As taught by O’Donnell, one of ordinary skill in the art would utilize and modify the above teaching into Lueders to obtain and achieve the device wherein a vertical line orthogonal to the first and second surfaces extends through both the first and second semiconductor dies as claimed, because a vertically stacked arrangement of galvanically isolated semiconductor dies that provides a more compact and highly integrated package configuration while maintaining isolation functionality [0080].
Thus, it would have been obvious to one of ordinary skill in the art before the effective filling date of the claimed invention to employ the teaching as taught by O’Donnell in combination with Lueders due to above reason.
Regarding claim 13, Lueders teaches an isolation device (900, FIGS. 9-10, [0055]), comprising:
a multi-level substrate (902 including 1000, 1002, and 1004 embedded within 1014, [0056-0057]) having opposing first (a surface portion of 902 associated with IC 910, [0056]; hereinafter ‘902S1’) and second surfaces (a surface portion of 902 associated with IC 920; hereinafter ‘902S2’), the multi-level substrate (902) including:
a first coil (winding 906, [0059, 0064]) in a first layer (1000, [0066]) of the substrate (902) that is closer to the first surface (902S1) than to the second surface (902S2), the first coil (906) having first (918-1, [0061]) and second terminals (918-2);
a second coil (winding 908, [0059, 0065]) in a second layer of the substrate (902) that is closer to the second surface (902S2) than to the first surface (902S1), the second coil (908) having third (932-1, [0061]) and fourth terminals (932-2); and
a dielectric material (1014, [0036, 0058]) covering the first (906) and second coils (908);
a first semiconductor die (910) coupled to the first (918-1) and second terminals (918-1) with a first set of solder bumps (solder balls, [0061-0062]);
a second semiconductor die (920) coupled to the third (932-1) and fourth terminals (932-2) with a second set of solder bumps (solder balls), the first (910) and second semiconductor dies (920) separated from each other by a second distance in the horizontal direction (910 and 920 are separated by a first distance by a second direction in the horizontal direction, FIGS. 9 and 10);
conductive terminals (948, [0057]) coupled to the multi-level substrate (902, wherein 948 coupled to 902, [0063]); and
a mold compound (1012, [0056]) covering the multi-level substrate (902), the first (910) and second semiconductor dies (920), and the conductive terminals (948, wherein 1012 encapsulates IC package 900 covering 902, 910, 920, and 948, [0056]), the conductive terminals exposed to an exterior of the mold compound (948 exposed at an exterior surface of the package 900 for mounting to an external circuit support structure, [0063]).
Lueders does not teach the isolation device wherein the first and second semiconductor dies are separated from each other by a first distance in the vertical direction.
O’Donnell teaches an isolation device wherein the first and second semiconductor dies are separated from each other by a first distance in the vertical direction (second semiconductor die 1320 is stacked above first semiconductor die 1310 with substrate 1330 disposed therebetween, thereby defining a separation distance between dies 1310 and 1320 in a vertical direction, FIG. 13, [0113]).
As taught by O’Donnell, one of ordinary skill in the art would utilize and modify the above teaching into Lueders to obtain and achieve the isolation device wherein the first and second semiconductor dies are separated from each other by a first distance in the vertical direction as claimed, because alternative die-placement configurations for isolated semiconductor dies include laterally separated dies (FIG. 12(a)) and vertically stacked dies (FIG. 13), indicating that the relative positioning of the semiconductor dies is a matter of design choice that may be varied while maintaining electrical isolation [0106, 0113, 0173]. Further, it has been held that that rearranging part of an invention involves only routine skill in the art. In re Japikse, 86 USPQ 70.
Thus, it would have been obvious to one of ordinary skill in the art before the effective filling date of the claimed invention to employ the teaching as taught by O’Donnell in combination with Lueders due to above reason.
Regarding claim 14, Lueders in view of O’Donnell teaches the device of claim 13, wherein the dielectric material comprises a build-up film (Lueders: 1014 comprises Ajinomoto build-up film (ABF), [0036, 0058]).
Regarding claim 15, Lueders in view of O’Donnell teaches the device of claim 13, wherein the substrate is not a printed circuit board (PCB) (Lueders: 902 is distinct from an external PCB and is configured to be mounted thereto through contact pads 948, [0063]) and the dielectric material is a solid dielectric material and not air (1014 comprises Ajinomoto build-up film (ABF), [0036, 0058]).
Regarding claim 16, Lueders in view of O’Donnell teaches the device of claim 13, wherein device sides of the first and second semiconductor dies in which circuitry is formed face the substrate (Lueders: device sides of 910 and 920 having circuitry formed therein face circuit support structure 902, [0061-0062]).
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to JIYOUNG OH whose telephone number is (703)756-5687. The examiner can normally be reached Monday-Friday, 9AM-5PM EST.
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/JIYOUNG OH/Examiner, Art Unit 2818
/DUY T NGUYEN/Primary Examiner, Art Unit 2818 6/11/26
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