Prosecution Insights
Last updated: April 19, 2026
Application No. 18/397,756

SEMICONDUCTOR DEVICE

Non-Final OA §102
Filed
Dec 27, 2023
Examiner
LINDSEY, COLE LEON
Art Unit
2812
Tech Center
2800 — Semiconductors & Electrical Systems
Assignee
Fuji Electric Co. Ltd.
OA Round
1 (Non-Final)
89%
Grant Probability
Favorable
1-2
OA Rounds
2y 11m
To Grant
99%
With Interview

Examiner Intelligence

Grants 89% — above average
89%
Career Allow Rate
103 granted / 116 resolved
+20.8% vs TC avg
Moderate +13% lift
Without
With
+12.8%
Interview Lift
resolved cases with interview
Typical timeline
2y 11m
Avg Prosecution
34 currently pending
Career history
150
Total Applications
across all art units

Statute-Specific Performance

§103
55.8%
+15.8% vs TC avg
§102
27.2%
-12.8% vs TC avg
§112
15.1%
-24.9% vs TC avg
Black line = Tech Center average estimate • Based on career data from 116 resolved cases

Office Action

§102
CTNF 18/397,756 CTNF 97480 Notice of Pre-AIA or AIA Status 07-03-aia AIA 15-10-aia The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA. Claim Rejections - 35 USC § 102 07-07-aia AIA 07-07 The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action: A person shall be entitled to a patent unless – 07-08-aia AIA (a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention. 07-15 AIA Claim 12 is rejected under 35 U.S.C. 102( a)(1 ) as being anticipated by Kato et al. (US20180166549A1, hereinafter Kato ) . Regarding claim 12 , Kato discloses a semiconductor device, comprising: a semiconductor chip including at a front surface thereof (Fig. 2 semiconductor element 30), an upper electrode having chip lateral surfaces that surround an outer periphery of the upper electrode in a plan view of the semiconductor device (Fig. 4 surface electrode 82 on upper surface of semiconductor element 30 with plated layers 38-1/38-2 that have outer surfaces surrounding the periphery as shown in fig. 3d), the chip lateral surfaces including a first lateral surface (Fig. 3 plated layers 38-1 has leftmost lateral surface); a lead frame including a bonding part and a rising part (Fig. 4 metal connecting plate has horizontal portion adjacent to solder 80 and rising portion 63), the bonding part having terminal lateral surfaces that surround an outer periphery of the bonding part in the plan view (Fig. 3 metal connecting plate 60 has a front surface and lateral surfaces that surround the outer periphery in a plan view), the terminal lateral surfaces including a second lateral surface (Fig. 3 leftmost lateral surface of the surfaces surrounding the outer periphery is a second lateral surface on metal connecting plate 60), the bonding part being joined to the upper electrode such that the first lateral surface faces the second lateral surface (Fig. 3 leftmost lateral surface of plated part 38-1 faces leftmost lateral surface of the surfaces surrounding the outer periphery is a second lateral surface on metal connecting plate 60), the rising part extending upward with respect to the electrode front surface from the first lateral surface (Fig. 4 rising portion 63 rises upward); and a bonding member joining the upper electrode to the bonding part (Kato fig. 4 solder 80), wherein: the rising part has a stepped shape in a side view of the semiconductor device so as to extend upward with respect to the electrode front surface from the second lateral surface (Fig. 4 rising portion 63 has a stepped shape in a side view and extends upwards with respect to surface electrode 82) . Allowable Subject Matter 12-151-07 AIA 07-97 12-51-07 Claim s 1-11 allowed. 13-03-01 AIA The following is a statement of reasons for the indication of allowable subject matter: Regarding claim 1 and its dependent claims . The closest prior art (US20180166549A1, US20130187259A1, US20160181221A1) teaches a semiconductor device, comprising: a semiconductor chip (Kato fig. 2 semiconductor element 30) including at a chip front surface thereof, an upper electrode having an electrode front surface and electrode lateral surfaces that surround an outer periphery of the upper electrode in a plan view of the semiconductor device (Kato fig. 4 surface electrode 82 on upper surface of semiconductor element 30 with plated layers 38-1/38-2 that have outer surfaces surrounding the periphery as shown in fig. 3d), the electrode lateral surfaces including a first lateral surface (Kato fig. 3 plated layers 38-1 has leftmost lateral surface); a lead frame having a bonding part and a rising part (Kato fig. 4 metal connecting plate has horizontal portion adjacent to solder 80 and rising portion 63), the bonding part having a bonding front surface and terminal lateral surfaces that surround an outer periphery of the bonding part in the plan view (Kato fig. 3 metal connecting plate 60 has a front surface and lateral surfaces that surround the outer periphery in plan view), the terminal lateral surfaces including a second lateral surface (Kato fig. 3 leftmost lateral surface of the surfaces surrounding the outer periphery is a second lateral surface on metal connecting plate 60), the bonding part being joined to the electrode front surface of the upper electrode such that the second lateral surface faces the first lateral surface (Kato fig. 3 leftmost lateral surface of plated part 38-1 faces leftmost lateral surface of the surfaces surrounding the outer periphery is a second lateral surface on metal connecting plate 60), the rising part extending upward with respect to the electrode front surface from the second lateral surface (Kato fig. 4 rising portion 63 rises upward); and a bonding member joining the upper electrode to the bonding part (Kato fig. 4 solder 80). However, the closest prior art does not teach in combination with the other claimed elements wherein in a direction parallel to the electrode front surface, a first shortest distance between a center of the electrode front surface in the plan view and the second lateral surface is equal to or greater than 40% of a second shortest distance between the first lateral surface and the second lateral surface. Additionally, the closest prior art does not teach the above in combination with the further limitations of dependent claims. Examiner notes that while there are embodiments within the prior art, see Kato fig. 4, that teach a semiconductor device with a lead frame comprising a rising portion, examiner's search of the prior art did not find an embodiment nor any motivation to combine embodiments such that a first shortest distance between a center of the electrode front surface in the plan view and the second lateral surface is equal to or greater than 40% of a second shortest distance between the first lateral surface and the second lateral surface in addition with the other limitations of the claim. Examiner additionally notes pars. 57-58 of the specification which describes the difference in performance associated with the allowable subject matter . Conclusion Any inquiry concerning this communication or earlier communications from the examiner should be directed to COLE LEON LINDSEY whose telephone number is (571)272-4028. The examiner can normally be reached Monday - Friday, 8:00 a.m. - 5:00 p.m.. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Christine Kim can be reached at (571)272-8458. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /COLE LEON LINDSEY/Examiner, Art Unit 2812 /CHRISTINE S. KIM/Supervisory Patent Examiner, Art Unit 2812 Application/Control Number: 18/397,756 Page 2 Art Unit: 2812 Application/Control Number: 18/397,756 Page 3 Art Unit: 2812 Application/Control Number: 18/397,756 Page 4 Art Unit: 2812 Application/Control Number: 18/397,756 Page 5 Art Unit: 2812 Application/Control Number: 18/397,756 Page 6 Art Unit: 2812
Read full office action

Prosecution Timeline

Dec 27, 2023
Application Filed
Mar 06, 2026
Non-Final Rejection — §102 (current)

Precedent Cases

Applications granted by this same examiner with similar technology

Patent 12593630
PROCESS FOR MANUFACTURING A SILICON CARBIDE DEVICE AND SILICON CARBIDE DEVICE
2y 5m to grant Granted Mar 31, 2026
Patent 12575330
ORDERED ALLOY MAGNETIC TUNNEL JUNCTION WITH SIMPLIFIED SEED STRUCTURE
2y 5m to grant Granted Mar 10, 2026
Patent 12550407
SEMICONDUCTOR DEVICES WITH BACKSIDE VIA AND METHODS THEREOF
2y 5m to grant Granted Feb 10, 2026
Patent 12543538
TEMPORARY FIXATION LAYERED FILM AND PRODUCTION METHOD THEREFOR, TEMPORARY FIXATION LAYERED BODY, AND SEMICONDUCTOR DEVICE PRODUCTION METHOD
2y 5m to grant Granted Feb 03, 2026
Patent 12532501
STRUCTURE WITH BACK-GATE HAVING OPPOSITELY DOPED SEMICONDUCTOR REGIONS
2y 5m to grant Granted Jan 20, 2026
Study what changed to get past this examiner. Based on 5 most recent grants.

AI Strategy Recommendation

Get an AI-powered prosecution strategy using examiner precedents, rejection analysis, and claim mapping.
Powered by AI — typically takes 5-10 seconds

Prosecution Projections

1-2
Expected OA Rounds
89%
Grant Probability
99%
With Interview (+12.8%)
2y 11m
Median Time to Grant
Low
PTA Risk
Based on 116 resolved cases by this examiner. Grant probability derived from career allow rate.

Sign in with your work email

Enter your email to receive a magic link. No password needed.

Personal email addresses (Gmail, Yahoo, etc.) are not accepted.

Free tier: 3 strategy analyses per month