Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
DETAILED ACTION
Election/Restrictions
Applicant’s election without traverse of Group I (claims 1-13) in the reply filed on 5/4/26 is acknowledged. Claims 14-20 are withdrawn from further consideration pursuant to 37 CFR 1.142(b) as being drawn to a nonelected invention, there being no allowable generic or linking claim.
Title
The title of the invention is not descriptive. A new title is required that is clearly indicative of the invention to which the claims are directed. (see MPEP § 606.01).
This may result in slightly longer titles, but the loss in brevity of title will be more than offset by the gain in its informative value in indexing, classifying, searching, etc.
The following title is suggested:
"Semiconductor Package Including Dummy Semiconductor Chip Having Embedded Capacitor and Through-Via"
because it reflects the specific package structure disclosed and claimed, including the dummy semiconductor chip, through-via, and embedded capacitor.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1 and 5-10 are rejected under 35 U.S.C. 103 as being unpatentable over Radhakrishnan et al. (US 20230060727).
Regarding claim 1. Radhakrishnan teaches A semiconductor package comprising: "a structure" (conductive structure 110 and interconnect structure 132 underlying VR die 104 and passive die 122; Fig. 1);
"a first semiconductor chip disposed on an upper surface of the structure and electrically connected to the structure directly" (VR die 104 disposed on the upper surface of conductive structure 110/interconnect structure 132 and electrically connected thereto through conductive interconnections; Fig. 1, [0042]-[0043], [0051]-[0052]). Radhakrishnan further teaches that VR die 104 may comprise a substantially monocrystalline semiconductor, such as silicon or germanium, as a substrate on which active devices are fabricated using semiconductor processing methods ([0055]). Therefore, VR die 104 corresponds to the claimed first semiconductor chip.
Radhakrishnan teaches "a dummy semiconductor chip disposed on the upper surface of the structure and spaced apart from the first semiconductor chip, wherein the dummy semiconductor chip includes silicon" (passive die 122 disposed on the upper surface of conductive structure 110/interconnect structure 132 and laterally spaced apart from VR die 104; Fig. 1, [0050]).
Radhakrishnan further teaches that bridge die 122 may comprise a substantially monocrystalline semiconductor, such as silicon or germanium ([0055]). The claimed "dummy semiconductor chip" reasonably reads on passive die 122 because passive die 122 is a semiconductor die lacking active elements and functioning as a passive structure within the package ([0050]). Therefore, passive die 122 corresponds to the claimed dummy semiconductor chip, and the disclosed silicon semiconductor substrate satisfies the claimed silicon limitation.
But Radhakrishnan does not expressly teach "a capacitor disposed inside the dummy semiconductor chip."
However, Radhakrishnan teaches that embedded devices may include passive devices such as capacitors and decoupling capacitors ([0090]). Thus, Radhakrishnan expressly identifies capacitors and decoupling capacitors as suitable passive devices.
Thus, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to incorporate a capacitor into passive die 122 because Radhakrishnan expressly identifies capacitors and decoupling capacitors as suitable passive devices. Incorporating a capacitor into passive die 122 would have predictably provided known decoupling, power stabilization, impedance reduction, and noise reduction functions.
Regarding claim 5. Radhakrishnan teaches The semiconductor package of claim 1. Radhakrishnan teaches "the upper surface of the dummy semiconductor chip contacts a lower surface of the redistribution layer" (passive die 122 underlying redistribution layer 304 formed on interposer 302 extending continuously across passive die 122; Fig. 3, [0066]). Accordingly, the lower surface of the redistribution-layer structure is disposed on the upper surface of passive die 122.
Regarding claim 6. Radhakrishnan teaches The semiconductor package of claim 1. Radhakrishnan further teaches "a lower surface of the second through-via is coplanar with a lower surface of the dummy semiconductor chip, and wherein an upper surface of the second through-via is coplanar with the upper surface of the dummy semiconductor chip" (TSV 128 extending completely through passive die 122, wherein the lower end of TSV 128 is flush with the lower surface of passive die 122 and the upper end of TSV 128 is flush with the upper surface of passive die 122; Fig. 1).
Regarding claim 7. Radhakrishnan teaches The semiconductor package of claim 1. Radhakrishnan further teaches "a second semiconductor chip disposed on an upper surface of the redistribution layer and electrically connected to the redistribution layer directly" (load die 102 disposed on interposer 302 including redistribution layer 304 and electrically connected thereto through conductive interconnections; Figs. 1 and 3, [0041], [0066]). Radhakrishnan further teaches that load die 102 may comprise a substantially monocrystalline semiconductor substrate on which active devices are fabricated using semiconductor processing methods ([0055]). Therefore, load die 102 corresponds to the claimed second semiconductor chip.
Regarding claim 8. Radhakrishnan teaches The semiconductor package of claim 1. Radhakrishnan further teaches "an upper package substrate disposed on an upper surface of the redistribution layer" (upper substrate/package structure 608 disposed above and electrically connected to redistribution layer 604 through conductive connectors 606; Fig. 6; [0070]);
"a second semiconductor chip disposed on an upper surface of the upper package substrate" (semiconductor die 102 disposed on an upper surface of upper substrate/package structure 608; Fig. 6; [0070]).
Regarding claim 9. Radhakrishnan teaches The semiconductor package of claim 1. Radhakrishnan teaches: "the upper surface of the first semiconductor chip contacts the redistribution layer" (first semiconductor chip 104 having an upper surface facing and contacting redistribution layer 304 through interposer 302 in Fig. 3, and similarly contacting redistribution layer 604 through conductive interconnection structure 602 in Fig. 6; Figs. 3 and 6; [0066], [0070]);
"the first semiconductor chip is directly and electrically connected to the redistribution layer" (first semiconductor chip 104 electrically connected to redistribution layer 304/604 through conductive interconnection structures disposed directly between the chip and redistribution layer, including conductive structures 130 and conductive interconnection structure 602, thereby providing a direct electrical connection between first semiconductor chip 104 and the redistribution layer; Figs. 3 and 6; [0066], [0070]).
Regarding claim 10. Radhakrishnan teaches The semiconductor package of claim 1. Radhakrishnan further teaches: "the upper surface of the first semiconductor chip, the upper surface of the dummy semiconductor chip, and the upper surface of the molding layer are coplanar" (Fig. 3 illustrates first semiconductor chip 104, dummy semiconductor chip 122, and molding layer 138 having a common upper surface upon which interposer 302 and redistribution layer 304 are subsequently formed. A person of ordinary skill in the art would have understood that the upper surfaces of first semiconductor chip 104, dummy semiconductor chip 122, and molding layer 138 are planarized and coplanar to permit formation of interposer 302 across the respective structures; Fig. 3; [0066]).
Claims 2-4 and 11 are rejected under 35 U.S.C. 103 as being unpatentable over Radhakrishnan et al. (US 20230060727) in view of Chen et al. (US 20190067244).
Regarding claim 2. Radhakrishnan teaches The semiconductor package of claim 1. But Radhakrishnan does not expressly teach that a first insulating layer disposed on the upper surface of the structure; a base material layer disposed on the first insulating layer and including silicon; and a second insulating layer disposed on the base material layer, and wherein the second through-via extends through the first insulating layer, the base material layer, and the second insulating layer in the vertical direction.
However, Chen teaches a second die 103 that may be a dummy die ([0033]). Chen further teaches a second dielectric layer 103b, a silicon substrate 103a disposed on the second dielectric layer 103b, a third dielectric layer 103f disposed on the silicon substrate 103a, and a through-substrate via 103h extending through the second dielectric layer 103b, the silicon substrate 103a, and the third dielectric layer 103f (Fig. 1; [0034]-[0043]). Chen further teaches that second die 103 may comprise electrical circuits including capacitors ([0033]).
Thus, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify dummy semiconductor chip 122 of Radhakrishnan to include the semiconductor die structure taught by Chen because Chen teaches a known TSV-containing semiconductor die structure including insulating layers, a silicon substrate, and a through-substrate via suitable for vertical electrical routing. Such modification would have predictably provided a known semiconductor die structure while maintaining the functionality of the passive die of Radhakrishnan.
Regarding claim 3. Radhakrishnan in view of Chen teaches The semiconductor package of claim 2. Chen teaches "the capacitor is disposed inside the base material layer" (Chen teaches that second die 103 may comprise electrical circuits including capacitors, and that second die 103 includes silicon substrate 103a; Fig. 1; [0033]).
Thus, it would have been obvious to incorporate a capacitor into the silicon base material layer because Chen expressly teaches capacitors as suitable circuitry within second die 103. Incorporating such capacitor structures would have predictably provided known decoupling, power stabilization, impedance reduction, and noise reduction functions.
Regarding claim 4. Radhakrishnan in view of Chen teaches The semiconductor package of claim 3. Chen teaches that second die 103 may comprise electrical circuits including capacitors ([0033]). Chen further teaches that second dielectric layer 103b includes several layers of dielectric material stacked over each other ([0035]). Chen additionally teaches that silicon substrate 103a is disposed adjacent second dielectric layer 103b (Fig. 1; [0034]).
Thus, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to employ one or more dielectric layers of second dielectric layer 103b as an insulating layer between the capacitor and silicon substrate 103a because Chen expressly teaches both capacitors within second die 103 and a multi-layer dielectric structure 103b associated with the die. Utilizing one or more dielectric layers of 103b for the known purpose of electrically isolating passive devices from semiconductor substrates would have been a predictable variation yielding no more than the expected result of electrical insulation between the capacitor and substrate, thereby reducing leakage current, preventing unintended electrical interaction with the substrate, improving capacitor reliability, and enabling proper capacitor operation.
Regarding claim 11. Radhakrishnan teaches The semiconductor package of claim 1. But Radhakrishnan does not expressly teach: "a vertical level of the upper surface of the dummy semiconductor chip and a vertical level of the upper surface of the molding layer are higher than a vertical level of the upper surface of the first semiconductor chip."
However, Chen teaches a semiconductor package including first die 102, second die 103, and molding compound 104 (Fig. 1). Chen further teaches that second die 103 may be a dummy die ([0033]). Figure 1 illustrates that the upper surface of second die 103 and the upper surface of molding compound 104 are disposed at a higher vertical level than the upper surface of first die 102.
Thus, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to employ the relative die-height arrangement taught by Chen in the semiconductor package of Radhakrishnan because Chen teaches a known package configuration in which a dummy die and molding compound extend above an adjacent semiconductor die. Adopting the known arrangement of Chen would have predictably facilitated package routing, die integration, and package formation while maintaining the functionality of the semiconductor package.
Claims 12-13 are rejected under 35 U.S.C. 103 as being unpatentable over Radhakrishnan et al. (US 20230060727) in view of Park et al. (US 20220068904).
Regarding claim 12. Radhakrishnan teaches The semiconductor package of claim 1. Radhakrishnan does not expressly teach: "a first stack insulating layer disposed on the upper surface of the structure, the first stack insulating layer spaced apart from the sidewall of the first semiconductor chip and the sidewall of the dummy semiconductor chip in the horizontal direction; and a second stack insulating layer disposed on the first stack insulating layer, the second stack insulating layer spaced apart from the sidewall of the first semiconductor chip and the sidewall of the dummy semiconductor chip in the horizontal direction, wherein the molding layer covers the first stack insulating layer, the second stack insulating layer, and the first semiconductor chip, and wherein the first through-via extends through the first stack insulating layer, the second stack insulating layer, and the molding layer in the vertical direction."
However, Park teaches "a first stack insulating layer disposed on the upper surface of the structure" (Park teaches first upper passivation layer 120 disposed on first substrate 100; Fig. 2; [0020]-[0022]);
"the first stack insulating layer spaced apart from the sidewall of the first semiconductor chip and the sidewall of the dummy semiconductor chip in the horizontal direction" (Park teaches first upper passivation layer 120 extending laterally beyond semiconductor chip 200; Fig. 2);
"a second stack insulating layer disposed on the first stack insulating layer" (Park teaches second lower passivation layer 310 disposed above first upper passivation layer 120; Fig. 2; [0033]-[0035]);
"the second stack insulating layer spaced apart from the sidewall of the first semiconductor chip and the sidewall of the dummy semiconductor chip in the horizontal direction" (Park teaches second lower passivation layer 310 extending laterally beyond semiconductor chip 200; Fig. 2);
"wherein the molding layer covers the first stack insulating layer, the second stack insulating layer, and the first semiconductor chip" (Park teaches molding layer 250 covering semiconductor chip 200 and extending between passivation layers 120 and 310; Fig. 2; [0031], [0044]); and
"wherein the first through-via extends through the first stack insulating layer, the second stack insulating layer, and the molding layer in the vertical direction" (Park teaches conductive structure 240 extending vertically through first upper passivation layer 120, molding layer 250, and second lower passivation layer 310; Fig. 2; [0032]).
Thus, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to incorporate the stacked insulating layer arrangement of Park into the semiconductor package of Radhakrishnan because stacked insulating/passivation layers and vertical conductive structures were known for providing electrical insulation, structural support, and vertical electrical routing within semiconductor packages. Such modification would have predictably improved dielectric isolation and package reliability while maintaining the intended electrical interconnection functions of the package.
Regarding claim 13. Radhakrishnan in view of Park teaches The semiconductor package of claim 12. Park further teaches: "wherein the molding layer is disposed between the first and second stack insulating layers and the first semiconductor chip" (Park teaches molding layer 250, including molding portion 251, disposed between first upper passivation layer 120, second lower passivation layer 310, and semiconductor chip 200, as illustrated in Fig. 2 and described in [0031] and [0044]).
Thus, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to employ the same molding arrangement around the dummy semiconductor chip of Radhakrishnan because molding material conventionally surrounds and encapsulates semiconductor package components to provide mechanical support, structural integrity, and environmental protection.
Conclusion
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/Changhyun Yi/Primary Examiner, Art Unit 2812
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