Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 11 and 14 is/are rejected under 35 U.S.C. 103 as being unpatentable over Zhao (Pub. No.: US 2021/0391353) filed in the IDS on 02/27/2023 in view of JEON (Pub. No.: US 2020/0365213) and further in view of Zhang (Patent No.: US 11158622) and Chu (Pub. No.: US 2002/0109231).
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Re claim 11, Zhao, FIGS. 3A-3B teaches a memory device, comprising:
a stack structure comprising a vertically alternating sequence of insulative structures (324, ¶ [0052]) and conductive structures (326);
at least one source structure (332) underlying the stack structure;
cell pillar structures (310, [0055]) vertically extending through the stack structure and coupled to the at least one source structure;
cell contact structures (312) coupled to cell pillar structures;
conductive plug structures (336+340+342) in physical contact with the cell contact structures (312), each of the conductive plug structures (336+340+342) comprising:
a first portion (336) having a first variable width throughout a first vertical height of the first portion,
a second portion (340) having an upper end and a lower end opposite to the upper end, the lower end of the second portion in direction contact with the first portion (336) and having a second width (with of lower end 340) less than the first width (top horizontal width) of the first portion (upper most portion of 336);
a third portion (342) in direction contact with the upper end of the second portion (340) and having a third width throughout a third vertical height of the third portion (340), the third width of the third portion (horizontal width of 342) greater than the first width of the first portion (horizontal width of 336);
digit line contact structures (bit line, [0056]) overlying and coupled to the conductive plug structures.
Zhao fails to teach a first portion (336) having a first width throughout a first vertical height of the first portion,
digit line contact structures in physical contact with the conductive plug structures; and
digit line structures coupled to the digit line contact structures.
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JEON, FIG. 17 [as shown above] teaches a first portion [FP] having a first width throughout a first vertical height of the first portion,
digit line contact structures (4371c/4372c/4271c) in physical contact with the conductive plug structures ([FP]/[SP]/[TP]), and
digit line structures (4240c/4230c/4220c) coupled to the digit line contact structures (4371c/4372c/4271c).
It would have been obvious for a person of ordinary skill in the art before the effective filing date of the claim invention to include the above said teaching for the purpose of enhancing the connectivity as taught by JEON, [0004].
Moreover, Zhao fails to teach the lower end of the second portion having a second width equal to the first width of the first portion.
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Zhang teaches the lower end of the second portion ([LESP], FIG. 1C [as shown above]) having a second width equal to the first width of the first portion [FP].
It would have been obvious for a person of ordinary skill in the art before the effective filing date of the claim invention to include the above said teaching for the purpose of addressing the density limitation in planar memory cells as taught by Zhang, BACKGROUND.
Finally, Zhao fails to teach the second portion exhibiting arcuate sidewalls having a concave shape.
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Chu teaches the second portion exhibiting arcuate sidewalls having a concave shape [SP].
It would have been obvious for a person of ordinary skill in the art before the effective filing date of the claim invention to include the above said teaching for the purpose of improving the integration and performance of semiconductor devices as taught by Chu, [0004].
Re claim 14, Zhao, FIGS. 3A-3B teaches an electronic system, comprising:
at least one microelectronic device structure comprising:
vertically extending strings of memory cells (310, [0055]) coupled to access line structures and at least one source structure;
conductive structures (336+340+342) overlying and coupled to the vertically extending strings of memory cells, each of the conductive structures comprising:
a lower portion having a first width (336);
an upper portion (342) having a second width greater than the first width; and
an intervening portion (340) having a lower end abutting the lower portion and an upper end abutting the upper portion.
digit line structures (bit line, [0056]) coupled to the digit line contact structures (336+340+342).
Zhao fails to teach an input device;
an output device;
a processor device operably coupled to the input device and the output device; and a memory device operably coupled to the processor device and comprising at least one microelectronic device structure comprising:
the lower end of the intervention portion having a third width equal to the first width of the lower portion; and the upper end of the intervention portion having a fourth width equal to the second width of the upper portion
digit line contact structures in physical contact with the conductive plug structures; and
digit line structures coupled to the digit line contact structures.
JEON, FIG. 17 [as shown above] teaches an input device (530, FIGS. 1-2);
an output device (530);
a processor device (560) operably coupled to the input device and the output device; and a memory device (300) operably coupled to the processor device and comprising at least one microelectronic device structure comprising:
the upper end of the intervention portion [SP] having a fourth width equal to the second width of the upper portion [TP];
digit line contact structures (4371c/4372c/4271c) in physical contact with the conductive plug structures ([FP]/[SP]/[TP]); and
digit line structures (4240c/4230c/4220c) coupled to the digit line contact structures (4371c/4372c/4271c).
It would have been obvious for a person of ordinary skill in the art before the effective filing date of the claim invention to include the above said teaching for the purpose of enhancing the connectivity as taught by JEON, [0004].
Moreover, Zhao fails to teach the lower end of the intervention portion having a third width equal to the first width of the lower portion.
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Zhang teaches the lower end of the intervention portion ([LESP], FIG. 1C [as shown above]) having a third width equal to the first width of the lower portion [FP].
It would have been obvious for a person of ordinary skill in the art before the effective filing date of the claim invention to include the above said teaching for the purpose of addressing the density limitation in planar memory cells as taught by Zhang, BACKGROUND.
Finally, Zhao fails to teach the intervening portion exhibiting arcuate sidewalls having a concave shape.
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Chu teaches the intervening portion exhibiting arcuate sidewalls having a concave shape [SP].
It would have been obvious for a person of ordinary skill in the art before the effective filing date of the claim invention to include the above said teaching for the purpose of improving the integration and performance of semiconductor devices as taught by Chu, [0004].
Claim(s) 11, 13-15 and 20 is/are rejected under 35 U.S.C. 103 as being unpatentable over LEE (Pub. No.: US 2017/0287930) in view of JEON.
Re claim 11, LEE, FIG. 13 teaches a memory device, comprising:
a stack structure comprising a vertically alternating sequence of insulative structures (ILD, ¶ [0054]) and conductive structures (EL);
at least one source structure (15, [0116]) underlying the stack structure;
cell pillar structures (VS1/HS1/DVS/DSP, [0073]) vertically extending through the stack structure and coupled to the at least one source structure;
cell contact structures (PAD) coupled to cell pillar structures;
conductive plug structures (LCP/SBL1/UCP) in physical contact with the cell contact structures (PAD), each of the conductive plug structures (LCP/SBL1/UCP) comprising:
a first portion (LCP) vertically adjacent to the respective cell contact structure and having a first width throughout a first vertical height of the first portion;
a second portion (SBL1) overlying the first portion, the lower end of the second portion in direct contact with the first portion (LCP);
a third portion (UCP) in direct contact with the second portion and having a third vertical height, the third portion exhibiting a third substantially uniform horizontal width (UCP) throughout the third vertical height;
digit line contact structures (BL1) in physical contact with the conductive plug structures (LCP/SBL1/UCP),
LEE fails to teach the lower end of the second portion having a second width equal to the first width of the first portion, the second portion exhibiting arcuate sidewalls having a concave shape;
the third width of the third portion greater than the first width of the first portion; and digit line structures coupled to the digit line contact structures.
JEON, FIG. 17 [as shown above] teaches the third width of the third portion [TP] greater than the first width of the first portion [FP]; and
digit line structures (4240c/4230c/4220c) coupled to the digit line contact structures (4371c/4372c/4271c).
It would have been obvious for a person of ordinary skill in the art before the effective filing date of the claim invention to include the above said teaching for the purpose of enhancing the connectivity as taught by JEON, [0004].
Moreover, LEE/JEON fails to teach the lower end of the second portion having a second width equal to the first width of the first portion.
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Zhang teaches the lower end of the second portion ([LESP], FIG. 1C [as shown above]) having a second width equal to the first width of the first portion [FP].
It would have been obvious for a person of ordinary skill in the art before the effective filing date of the claim invention to include the above said teaching for the purpose of addressing the density limitation in planar memory cells as taught by Zhang, BACKGROUND.
Finally, LEE fails to teach the second portion exhibiting arcuate sidewalls having a concave shape.
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Chu teaches the second portion exhibiting arcuate sidewalls having a concave shape
It would have been obvious for a person of ordinary skill in the art before the effective filing date of the claim invention to include the above said teaching for the purpose of improving the integration and performance of semiconductor devices as taught by Chu, [0004].
Re claim 13, in the combination, LEE, FIG. 13 teaches the memory device of claim 11, further comprising a base structure vertically underlying the stack structure and comprising a control logic circuitry (GST of FIGS. 2) coupled to the at least one source structure, the digit line structures (BT1/BT2), and the conductive structures (EL) of the stack structure.
Re claim 14, LEE, FIG. 11 teaches an electronic system, comprising:
an input device (5, FIG. 1);
an output device (2/3);
a processor device (5) operably coupled to the input device and the output device; and
a memory device operably coupled to the processor device and comprising at least one microelectronic device structure comprising:
vertically extending strings of memory cells (MCT of FIG. 2 or DS of FIG. 11, [0048]) coupled to access line structures and at least one source structure;
conductive structures (PAD/LCP/SEL1) overlying and coupled to the vertically extending strings of memory cells, each of the conductive structures comprising:
a lower portion (PAD) having a first width;
an upper portion (SBL1) having a second width greater than the first width;
an intervening portion (LCP) between the lower portion and the upper portion; and
digit line contact structures (BT1/BT2/UCP) in physical contact with the conductive structures (PAD/SBL1/LCP).
However, LEE fails to teach a lower portion having a first width;
an upper portion having a second width greater than the first width; and
an intervening portion having a lower end abutting the lower portion and an upper end abutting the upper portion, the intervening portion exhibiting arcuate sidewalls having a concave shape, the lower end of the intervention portion having a third width equal to the first width of the lower portion, the upper end of the intervention portion having a fourth width equal to the second width of the upper portion; and digit line structures coupled to the digit line contact structures.
JEON, FIG. 17 [as shown above] teaches a lower portion [FP] having a first width;
an upper portion [TP] having a second width greater than the first width [FP]; and
an intervening portion [SP] having a lower end abutting the lower portion and an upper end abutting the upper portion, the upper end of the intervention portion [SP] having a fourth width equal to the second width of the upper portion [TP]; and
digit line structures (4240c/4230c/4220c) coupled to the digit line contact structures (4371c/4372c/4271c).
It would have been obvious for a person of ordinary skill in the art before the effective filing date of the claim invention to include the above said teaching for the purpose of enhancing the connectivity as taught by JEON, [0004].
Moreover, LEE/JEON fails to teach the lower end of the intervention portion having a third width equal to the first width of the lower portion.
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Zhang teaches the lower end of the intervention portion ([LESP], FIG. 1C [as shown above]) having a third width equal to the first width of the lower portion [FP].
It would have been obvious for a person of ordinary skill in the art before the effective filing date of the claim invention to include the above said teaching for the purpose of addressing the density limitation in planar memory cells as taught by Zhang, BACKGROUND.
Finally, LEE/JEON fails to teach the intervening portion exhibiting arcuate sidewalls having a concave shape.
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Chu teaches the intervening portion exhibiting arcuate sidewalls having a concave shape [SP].
It would have been obvious for a person of ordinary skill in the art before the effective filing date of the claim invention to include the above said teaching for the purpose of improving the integration and performance of semiconductor devices as taught by Chu, [0004].
Re claim 15, LEE, FIG. 11 teaches the electronic system of claim 14, wherein the memory device comprises a 3D NAND Flash memory device (Abstract).
Re claim 20, in the combination, LEE, FIG. 13 teaches the electronic system of claim 14, wherein each of the digit line contact structures (BL1/BL1/UCP) has respectively having a horizontal center offset from a horizontal center of a respective one of the conductive structures (PAD/LCP/SBL1) in physical contract therewith.
Claim(s) 12 and 16-19 is/are rejected under 35 U.S.C. 103 as being unpatentable over LEE in view of JEON/Zhang/Chu and further in view of Zhu (Pub. No.: US 20210020566) filed in the IDS on 02/27/2023.
LEE/JEON teaches all the limitation of claim 11.
LEE/JEON fails to teach the limitation of claim 12.
Zhu teaches a dielectric oxide material (top most dielectric layer 108, FIG. 1A, ¶ [0031]) overlying the stack structure and horizontally adjacent the first horizontal boundaries of the first portion (122) of each of the conductive plug structures;
a dielectric nitride material (124/126, [0035]) on the dielectric oxide material and horizontally adjacent second horizontal boundaries of the second portion (128) of each of the conductive plug structures; and
an additional dielectric oxide material (132, [0039]) on the dielectric nitride material and horizontally adjacent third horizontal boundaries of the third portion (134) of each of the conductive plug structures.
It would have been prima facie obvious to one of ordinary skill in the art at the time the invention was made to include the above said teaching for the purpose of providing an electrical isolation layer and preventing the electrical short as taught by Zhu.
Re claim 16, LEE/JEON/Zhang/Chu teaches all the limitation of claim 14.
LEE/JEON fails to teach the limitation of claim 16.
Zhu, FIG. 1A teaches a first dielectric material (top most dielectric layer 108, ¶ [0030]) vertically overlying the stack structure and in physical contact with sidewalls of the lower portion (122) each of the conductive structures;
a second dielectric material (124/126) vertically overlying and having a different material composition than the first dielectric material, the second dielectric material in physical contact with sidewalls of the intervening portion (128) of each of the conductive structures; and
a third dielectric material (132, [0039]) vertically overlying and having a different material composition than the second dielectric material, the third dielectric material in physical contact with sidewalls of the upper portion (134) of each of the conductive structures.
It would have been prima facie obvious to one of ordinary skill in the art at the time the invention was made to include the above said teaching for the purpose of providing an electrical isolation layer and preventing the electrical short as taught by Zhu.
Re claim 17, in the combination, Zhu, FIG. 1A teaches the electronic system of claim 16, wherein:
the upper portion of each of the conductive structures (134) is substantially confined within a vertical span of the third dielectric material (132); and
the intervening portion of each of the conductive structures (128) is substantially confined within a vertical span of the second dielectric material (124/126).
Re claim 18, in the combination, Zhu, FIG. 1A teaches the electronic system of claim 16, wherein:
the first dielectric material is SiO2 (108, FIG. 1A, ¶ [0031]);
the second dielectric material is Si3N4 (124/126, [0035]); and
the third dielectric material is additional SiO2 (132, [0039]).
Re claim 19, in the combination, Fay, FIG. 7 teaches the electronic system of claim 16, wherein:
the sidewalls of the lower portion of each of the conductive structures vertically extend in substantially linear paths (120);
the sidewalls of the upper portion of each of the conductive structures vertically extend in additional substantially linear paths (106); and
the sidewalls of the intervening portion of each of the conductive structures vertically extend in curved paths (110/108).
Response to Arguments
Applicant's arguments with respect to claims 11-20 on the remarks filed on 07/06/2026 have been considered but are moot due to a new ground of rejection.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to TONY TRAN whose telephone number is (571)270-1749. The examiner can normally be reached Monday-Friday, 8AM-5PM, EST.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Britt Hanley can be reached on 571-270-3042. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/TONY TRAN/Primary Examiner, Art Unit 2893
Prosecution Insights