DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Objections
Claim 20 is objected to because of the following informalities:
Claim 20 line 4, the words “the six control transistor” should read –the sixth control transistor–
Appropriate correction is required.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim 1-4 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Chen Publication No. US 2007/0091530.
Regarding claim 1, Chen discloses an electrostatic discharge (ESD) protection circuit [Fig. 5, ESD protection circuit 500], coupled between a first voltage terminal [Fig. 5, Pad 510] and a second voltage terminal [Fig. 5, VSS], and comprising:
a main transistor [Fig. 5, transistor 530], having a first terminal, a second terminal, and a control terminal, wherein the first terminal of the main transistor is coupled to the second voltage terminal, and the second terminal of the main transistor is coupled to the first voltage terminal [Fig. 5, drain and source terminals of 530 are coupled to 510 and VSS as shown];
a first resistor element [Fig. 5, resistor RG] having a first terminal and a second terminal, wherein the first terminal of the first resistor element is coupled to the first voltage terminal [Fig. 5, top terminal of RG is coupled to the pad 510]; and
a control circuit [Fig. 5, inverter comprising transistors 521 and 520 as shown] having a first terminal, a second terminal, an input terminal and an output terminal, wherein the first terminal of the control circuit is coupled to the first voltage terminal [Fig. 5, top terminal of 521 is coupled to 510], the second terminal of the control circuit is coupled to the second voltage terminal [Fig. 5, bottom terminal of 520 is coupled to VSS], the input terminal of the control circuit is coupled to the second terminal of the first resistor element [Fig. 5, the input terminal of the inverter at the gates is coupled to the bottom terminal of the resistor RG], the output terminal of the control circuit is coupled to the control terminal of the main transistor [Fig. 5, the output terminal of the inverter is coupled to the gate terminal of the transistor 530], and
the control circuit comprises:
a first control transistor [Fig. 5, transistor 521 Mp1] having a first terminal, a second terminal and a control terminal, wherein the first terminal of the first control transistor is coupled to the first terminal of the control circuit, and the control terminal of the first control transistor is coupled to the input terminal of the control circuit; and
a second control transistor [Fig. 5, transistor 520 Mn1] having a first terminal, a second terminal and a control terminal, wherein the first terminal of the second control transistor is coupled to the second terminal of the control circuit, the second terminal of the second control transistor is coupled to the second terminal of the first control transistor, and the control terminal of the second control transistor is coupled to the input terminal of the control circuit;
wherein when an ESD event occurs, a product of a capacitance value of a parasitic capacitance of the second control transistor [par. 0036 suggests that: “For improvement, the capacitor for the RC time constant is replaced with a parasitic capacitor C1 generated between the gate terminal 522 and the source terminal 526 of the NMOS transistor 520] and a resistance value of the first resistor element [Fig. 5, the resistance value of the resistor RG] is greater than a duration of the ESD event, and the control circuit is configured to turn on the main transistor so that an ESD current flows through the main transistor [par. 0035].
Regarding claim 2, Chen discloses that the main transistor is an N-type transistor [Fig. 5, main transistor Mn2 is a NMOS transistor], and a size of the main transistor is larger than a size of the second control transistor [Fig. 5: the main transistor serves as a high-current shunt path during an ESD event, while the inverter dries the gate to ensure the main transistor turns on quickly, therefore, the size of the main transistor 530 is inherently larger than the second control transistor 520 of the inverter].
Regarding claim 3, Chen discloses that when the ESD event occurs, the first control transistor is turned on, the second control transistor is turned off, and a potential at the output terminal of the control circuit is high to turn on the main transistor [par. 0035].
Regarding claim 4, Chen discloses that the first control transistor is a P-type transistor [Fig. 5, PMOS transistor MP1], and the second control transistor is an N-type transistor [Fig. 5, NMOS transistor NM1].
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 5 and 18-20 are rejected under 35 U.S.C. 103 as being unpatentable over Chen Publication No. US 2007/0091530, in view of Kato Patent No. US 9,263,884.
Regarding claim 5, Chen discloses an NMOS transistor as a main transistor. However, Chen does not disclose that the main transistor is a P-type transistor.
Kato discloses an ESD protection circuit, comprising an RC timer, an inverter, and a main discharge transistor, wherein the main transistor is a P-type transistor [Fig. 6, 53].
Chen and Kato are analogous electrostatic discharge protection circuits. It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention, to incorporate a PMOS transistor as a main transistor, into Chen, for the benefit of offering the advantage of simplified, low-cost driving circuitry as it turns on with a low signal rather than a boosted gate voltage.
Regarding claim 18, Kato discloses that
the control circuit [Fig. 2, 4] further comprises:
a fifth control transistor [Fig. 2, transistor 43] having a first terminal, a second terminal and a control terminal, wherein the first terminal of the fifth control transistor is coupled to the first terminal of the control circuit, the second terminal of the fifth control transistor is coupled to the output terminal of the control circuit, and the control terminal of the fifth control transistor is coupled to the second terminal of the first control transistor [Fig. 2, all terminals of the fifth transistor 43 are electrically coupled to the pad, ground, and other elements in the circuit]; and
a sixth control transistor [Fig. 2, transistor 44] having a first terminal, a second terminal and a control terminal, wherein the first terminal of the sixth control transistor is coupled to the second terminal of the control circuit, the second terminal of the sixth control transistor is coupled to the second terminal of the fifth control transistor, and the control terminal of the sixth control transistor is coupled to the second terminal of the second control transistor [Fig. 2, all terminals of the sixth transistor 44 are electrically coupled to the pad, ground, and other elements in the circuit].
Regarding claim 19, Kato discloses that when the ESD event occurs, the first control transistor is turned on [Fig. 2, PMOS 41 is turned on], the second control transistor is turned off [Fig. 2, NMOS 42 is turned off], the fifth control transistor is turned off [Fig. 2, PMOS 43 is turned off], the sixth control transistor is turned on [Fig. 2, NMOS 44 is turned on], a potential at the second terminal of the first control transistor and a potential at the second terminal of the second control transistor are high potentials, a potential at the output terminal of the control circuit is low to turn on the main transistor [col. 4 lines 42-62].
Regarding claim 20, Kato discloses that the main transistor is a P-type transistor [Fig. 6 is a PMOS transistor as shown], and a size of the main transistor is larger than a size of the first control transistor [Fig. 5: the main transistor serves as a high-current shunt path during an ESD event, while the inverter dries the gate to ensure the main transistor turns on quickly, therefore, the size of the main transistor 53 is obviously larger than the second control transistor 41 of the inverter], the first control transistor and the fifth control transistor are P-type transistors [Fig. 2, transistors 41 and 43 are PMOS transistors as shown], and the second control transistor and the sixth control transistor are N-type transistors [Fig. 2, 42 and 44 are NMOS transistors as shown].
Claims 8-10 are rejected under 35 U.S.C. 103 as being unpatentable over Chen Publication No. US 2007/0091530, in view of Lai et al. Publication No. US 2010/0328827.
Regarding claim 8, Chen does not disclose a pull-down circuit.
Lai discloses an ESD protection circuit, comprising: an RC timer, an inverter [Fig. 2, 120] and a main discharge transistor [Fig. 2, 115], and further comprise a pull-down circuit [Fig. 2, 140] coupled between the input terminal of the control circuit, the first voltage terminal and the second voltage terminal, wherein when the ESD event occurs, a potential at the input terminal of the control circuit is low [par. 0027].
Chen and Lai are analogous ESD protection circuits. It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention, to incorporate a pull-down circuit into Chen, for the benefit of preventing false triggering by keeping the input of the inverter low.
Regarding claim 9, Lai discloses that when a potential difference between the input terminal of the control circuit and the first voltage terminal is lower than a critical voltage, the potential at the input terminal of the control circuit changes from low to high to turn off the main transistor [during normal operation when there is no ESD event, the potential at the input terminal of the inverter is changed to high to turn of the main transistor 115; par. 0027].
Regarding claim 10, Lai discloses that the pull-down circuit is coupled to the first terminal and the second terminal of the first resistor element [Fig. 1, the pull-down circuit 140 is electrically coupled to VDD and the second terminal of the resistor 125 as shown].
Allowable Subject Matter
Claims 6-7 and 11-17 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The following is an examiner’s statement of reasons for allowance of claim 6: The prior art does not disclose that when the ESD event occurs, the first control transistor is turned off, the second control transistor is turned on, and a potential at the output terminal of the control circuit is low to turn on the main transistor. This feature in combination with the rest of the claim limitations is not anticipated or rendered obvious by the prior art of record.
The following is an examiner’s statement of reasons for allowance of claim 11: The prior art does not disclose that the pull-down circuit comprises: a third control transistor, wherein a first terminal of the third control transistor is coupled to the first terminal of the first resistor element, and a control terminal of the third control transistor is coupled to the input terminal of the control circuit; and a fourth control transistor, wherein a first terminal of the fourth control transistor is coupled to the second voltage terminal, a second terminal of the fourth control transistor is coupled to the input terminal of the control circuit, and a control terminal of the fourth control transistor is coupled to a second terminal of the third control transistor. This feature in combination with the rest of the claim limitations is not anticipated or rendered obvious by the prior art of record.
Conclusion
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DHARTI PATEL
Primary Examiner
Art Unit 2836
/DHARTI H PATEL/ Primary Examiner, Art Unit 2838
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