Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
DETAILED ACTION
This office action is in response to the Applicant Election filled on 06/02/2026. Currently, claims 1-120 are pending in the application.
Election/Restrictions
Applicant's election without traverse of Species I (Figures 1-5), claims 1-20, in the reply filed on 06/02/2026 is acknowledged, there being no allowable generic or linking claim.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claims 1, 6-7 and 14-20 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by ASHIDA et al (JP 2017079432 A). A machine English translation of ASHIDA is provided with this office action.
Regarding claim 1, Figure 2 of ASHIDA discloses a semiconductor device comprising:
a chip which has a main surface (top surface in Figure 2);
a first conductivity type channel region (13, p-type, Pages 3-4 of English translation) which is formed in a surface layer portion of the main surface;
a second conductivity type drift region (12, n-type) which is formed in the surface layer portion of the main surface so as to be adjacent to the channel region;
a gate insulating film (18) which covers the channel region (13) and the drift region (12) on the main surface; and
a polysilicon gate (19) which includes a second conductivity type first portion (20, n-poly) which faces the channel region across the gate insulating film and a first conductivity type second portion (21, p-poly) which faces the drift region (12) across the gate insulating film and forms a pn-junction portion with the first portion.
Regarding claim 6, Figure 2 of ASHIDA discloses that the semiconductor device according to claim 1, wherein the first portion (20) faces the channel region (13) and the drift region (12) across the gate insulating film (18).
Regarding claim 7, Figure 2 of ASHIDA discloses that the semiconductor device according to claim 1, wherein the pn-junction portion faces the drift region (12) across the gate insulating film (18).
Regarding claim 14, Figure 2 of ASHIDA discloses that the semiconductor device according to claim 1, further comprising: a field insulating film (17) which covers the drift region on the main surface; wherein the gate insulating film (18) has a thickness which is less than a thickness of the field insulating film (17) and continues to the field insulating film.
Regarding claim 15, Figure 2 of ASHIDA discloses that the semiconductor device according to claim 14, wherein the polysilicon gate (19) is led out on the field insulating film (17) from on the gate insulating film (18) and faces the drift region (12) across the field insulating film.
Regarding claim 16, Figure 2 of ASHIDA discloses that the semiconductor device according to claim 15, wherein the first portion (20) is formed only on the gate insulating film (18), and the second portion (21) is formed on the gate insulating film (18) and on the field insulating film (17).
Regarding claim 17, Figure 2 of ASHIDA discloses that the semiconductor device according to claim 1, further comprising: a second conductivity type source region (14, n+ type) which is formed in the surface layer portion of the main surface; and a second conductivity type drain (16, n+ type) region which is formed in the surface layer portion of the main surface at an interval from the source region; wherein the channel region (13) is formed in the surface layer portion of the main surface in a region on the source region side between the source region and the drain region, and the drift region (12) is formed in the surface layer portion of the main surface in a region between the drain region (16) and the channel region (13).
Regarding claim 18, Figure 2 of ASHIDA discloses that the semiconductor device according to claim 17 further comprising: a first conductivity type body region (13, p-type) which is formed in the surface layer portion of the main surface; and a second conductivity type well region (15, n-type) which is formed in the surface layer portion of the main surface at an interval from the body region; wherein the source region (14) is formed in a surface layer portion of the body region (13), the drain region (16) is formed in a surface layer portion of the well region (15), and the first portion (20) faces the body region (13) and the source region (14) across the gate insulating film (18).
Regarding claim 19, Figure 2 of ASHIDA discloses that the semiconductor device according to claim 1, further comprising: a region separation structure (not shown but anticipated to have a regions for different elements in the device wherein Figure 2 is a part of the device as shown in Figure 1) which is formed in the main surface so as to demarcate a part of the main surface as a device region; wherein the channel region and the drift region are formed in the device region.
Regarding claim 20, Figure 2 of ASHIDA discloses a semiconductor device comprising:
a chip which has a main surface (top surface in the Figure 2);
a first conductivity type channel region (13, p-type, pages 3-4 of the English translation) which is formed in a surface layer portion of the main surface;
a second conductivity type drift region (12, n-type) which is formed in the surface layer portion of the main surface so as to be adjacent to the channel region;
a gate insulating film (18) which covers the channel region (13) and the drift region (12) on the main surface;
a polysilicon gate (19) which covers the gate insulating film so as to face the channel region and the drift region across the gate insulating film; and
a pn-junction diode (3) which is formed inside the polysilicon gate so as restrict a carrier that moves from a portion of the polysilicon gate which is positioned on the channel region (13) to a portion of the polysilicon gate which is positioned on the drift region (12).
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102 of this title, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 2-5 are rejected under 35 U.S.C. 103 as being obvious over ASHIDA et al (JP 2017079432 A).
Regarding claims 2-5, Figure 2 of ASHIDA does not explicitly teach that the semiconductor device according to claim 1, wherein a gate potential is to be imparted to the first portion, and a potential other than the gate potential is to be imparted to the second portion. Or
The semiconductor device according to claim 1, wherein a potential difference between the first portion and the second portion is less than a threshold voltage of the pn-junction portion. Or
The semiconductor device according to claim 1, wherein a floating potential, a reference potential which serves as a reference of circuit operation, or a ground potential is to be imparted to the second portion. Or
The semiconductor device according to claim 1, wherein the second portion is formed in an electrically floating state.
However, these above limitation specify intended uses or field of uses, and are treated as non-limiting since it has been held that in device claims, intended use must result in a structural difference between the claimed invention and the prior art in order to patentably distinguish the claimed invention from the prior art. If the prior art structure is capable of performing the intended use, then it meets the claim. In re Casey, 152 USPQ 235 (CCPA 1967); In re Otto, 136 USPQ 458, 459 (CCPA 1963). Further, a claim containing a “recitation with respect to the manner in which a claimed apparatus is intended to be employed does not differentiate the claimed apparatus from a prior art apparatus” if the prior art apparatus teaches all the structural limitations of the claim. Ex Parte Masham, 2 USPQ 2d 1647 (Bd. Pat. App. & Inter. 1987).
Claims 8-13 are rejected under 35 U.S.C. 103 as being obvious over ASHIDA et al (JP 2017079432 A) in view of YOSHIMURA (JP 2014183231 A). A machine English translation of YOSHIMURA is provided with this office action.
Regarding claims 8-9, Figure 2 of ASHIDA does not teach that the semiconductor device according to claim 1, wherein the first portion has a first high concentration portion and a first low concentration portion which is lower in concentration than the first high concentration portion, and the second portion forms the pn-junction portion with the first low concentration portion of the first portion, wherein the second portion has a second high concentration portion and a second low concentration portion which is lower in concentration than the second high concentration portion and forms the pn-junction portion with the first low concentration portion.
However, YOSHIMURA is a pertinent art which teaches a semiconductor device with protective diode formed in the gate electrode. Figures 1-3 of YOSHIMURA teach such a device wherein the pn diode (9) has a n++ region under a silicide region 15 for connecting an electrode 22 with low resistance.
Thus, it would have been obvious to one of the ordinary skill in the art before the effective filing date of the claimed invention to modify the device of ASHIDA as claimed above according to the teaching of YOSHIMURA in order to lower the resistance at the connecting electrode for the diode in its anode and cathode layer region.
Regarding claims 10-13, Figure 2 of ASHIDA does not teach that the semiconductor device according to claim 1, further comprising: an insulating film which covers the pn-junction portion on the polysilicon gate, wherein the insulating film includes a removing portion which exposes a portion other than the pn-junction portion on the polysilicon gate, and further comprising: a gate silicide which covers a portion that is exposed from the removing portion at the polysilicon gate, and wherein the removing portion includes a first removing portion which exposes the first portion and a second removing portion which exposes the second portion, and the gate silicide incudes a first gate silicide which covers the first portion and a second gate silicide which covers the second portion.
However, YOSHIMURA is a pertinent art which teaches a semiconductor device with protective diode formed in the gate electrode. Figures 1-3 of YOSHIMURA teach such a device wherein the pn diode (9) has a n++ region under a silicide region 15 for connecting an electrode with low resistance. Figures 1-3 of YOSHIMURA further teach a silicide block layer 17 formed on the part of the diode 9, wherein the silicide block layer 17 block is formed on an exposed portion of the pn junction in order to form electrodes connecting the diodes with low resistance and further to form a field plate to reduce the electric field applied to the gate electrode.
Thus, it would have been obvious to one of the ordinary skill in the art before the effective filing date of the claimed invention to modify the device of ASHIDA as claimed above according to the teaching of YOSHIMURA in order to lower the resistance at the connecting electrode for the diode in its anode and cathode region, and further to form a field plate on the diode for controlling the electric field applied to the gate electrode.
Examiner Notes
A reference to specific paragraphs, columns, pages, or figures in a cited prior art reference is not limited to preferred embodiments or any specific examples. It is well settled that a prior art reference, in its entirety, must be considered for all that it expressly teaches and fairly suggests to one having ordinary skill in the art. Stated differently, a prior art disclosure reading on a limitation of Applicant's claim cannot be ignored on the ground that other embodiments disclosed were instead cited. Therefore, the Examiner's citation to a specific portion of a single prior art reference is not intended to exclusively dictate, but rather, to demonstrate an exemplary disclosure commensurate with the specific limitations being addressed. In re Heck, 699 F.2d 1331, 1332-33,216 USPQ 1038, 1039 (Fed. Cir. 1983) (quoting In re Lemelson, 397 F.2d 1006, 1009, 158 USPQ 275, 277 (CCPA 1968)). In re: Upsher-Smith Labs. v. Pamlab, LLC, 412 F.3d 1319, 1323, 75 USPQ2d 1213, 1215 (Fed. Cir. 2005); In re Fritch, 972 F.2d 1260, 1264, 23 USPQ2d 1780, 1782 (Fed. Cir. 1992); Merck& Co. v. BiocraftLabs., Inc., 874 F.2d 804, 807, 10 USPQ2d 1843, 1846 (Fed. Cir. 1989); In re Fracalossi, 681 F.2d 792,794 n.1, 215 USPQ 569, 570 n.1 (CCPA 1982); In re Lamberti, 545 F.2d 747, 750, 192 USPQ 278, 280 (CCPA 1976); In re Bozek, 416 F.2d 1385, 1390, 163 USPQ 545, 549 (CCPA 1969).
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to KHAJA AHMAD whose telephone number is (571)270-7991. The examiner can normally be reached on Monday-Friday, 8:00 AM - 5:00 PM (Eastern Time).
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/KHAJA AHMAD/Primary Examiner, Art Unit 2813
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