Election/Restrictions
Applicant’s election of Group I Species A in the reply filed 07/09/2026 is acknowledged, claims 9-11 are hereby withdrawn from consideration.
The applicant has included claim 4 in the listing of claims that read on the elected species. However, claim 4 is drawn to a multilayer interposer structure, specifically including a BEOL, a lower BEOL, and a backside interconnect layer. This feature appears to be drawn to Fig. 1B, previously indicated as non-elected Species 2. As best understood by the examiner, this feature is not present in elected Species 1 drawn to Fig. 1A. Therefore, claim 4 is hereby withdrawn (along with claims 9-11) and will not be treated on its merits.
Status of Claims
Claims 1-20 are pending.
Claims 4 and 9-11 are withdrawn from consideration.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claim 13 is rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Regarding Claim 13, claim 13 repeats the phrase “active interposer region” in the statement “wherein the active interposer region comprises a different number of layers than the active interposer region”. This phrase renders the claim indefinite, as the recited phrase is identical and could not have a different number of layers in the claimed device.
Under the broadest reasonable interpretation, the claim should read “wherein the active interposer region comprises a different number of layers than the passive interposer region”, in order to be consistent with the claimed elements in independent claim 12, and thus will be examined as such.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claims 1-3, 5-6, and 12-20 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by US 2022/0278032 A1 Pietambaram et al (herein “Pietambaram”).
Regarding Claim 1, Pietambaram discloses:
A semiconductor device (see generally Fig. 1A showing cross-section view of package structure #100 and Fig. 1B showing zoomed in portion of interconnection structure between device dies and nested interposer structure) comprising:
a chip (#100, Fig. 1A);
an active interposer (#140, Fig. 1A) comprising one or more active components ([0021]) in an active component layer (layer/space occupied by interposer structures #130 and #140, and interposer fill material #132);
a first chiplet (#120 left, [0026], Fig. 1A) that is mounted on the chip (#100) and above the active interposer (#140);
a second chiplet (#120 right, [0026], Fig. 1A) that is mounted on the chip (#100) and above the active interposer (#140); and
an interconnect layer (#141, #182, [0023]) having an interconnection (#182) that bridges (#141, [0026]) between the first chiplet (#120 left) and the second chiplet (#120 right) and is configured to transfer at least one of power and a signal ([0023]) from a bottom-side bump (#137, Fig. 1A) on a bottom side of the chip (#100) to at least one of the first chiplet (#120 left) and the second chiplet (#120 right), directly or indirectly, through a TSV (#134, #144) of the active interposer (#140).
Regarding Claim 2, Pietambaram discloses: The semiconductor device of claim 1:
Pietambaram further discloses:
wherein the chip (#100) comprises an interposer trench (#135, Fig. 1A) within which the active interposer (#140) is positioned; and
the semiconductor device further comprising an interposer fill material (#132) that fills a remaining portion of the interposer trench (#135) that is not filled by the active interposer (#140).
Regarding Claim 3, Pietambaram discloses: The semiconductor device of claim 2,
Pietambaram further discloses:
wherein the interposer fill material (#132) is selected from the group consisting of an organic material, an inorganic material, a hybrid material, and a combination of organic and inorganic material sequentially ([0052]-[0053]).
Regarding Claim 5, Pietambaram discloses: The semiconductor device of claim 1,
Pietambaram further discloses:
wherein the active interposer comprises silicon ([0053], with respect to Figs. 3A-3K showing method of manufacturing nested interposer).
Regarding Claim 6, Pietambaram discloses: The semiconductor device of claim 1,
Pietambaram further discloses:
wherein the active interposer (#140) comprises passive regions ([0023]) without active components, the passive regions comprising backside contacts (#143, [0023]: “…In an embodiment, the nested component 140 may include through component vias (TCVs) 144. The TCVs 144 may electrically couple the active surface 141 to pads 143 on the backside of the nested component 140.”).
Regarding Claim 12, Pietambaram discloses:
A semiconductor device (see generally Fig. 1A showing cross-section view of package structure #100 and Fig. 1B showing zoomed in portion of interconnection structure between device dies and nested interposer structure) comprising:
a chip (#100);
an active interposer region (middle section of interposer layer containing interposers #140) of an active interposer (#140, Fig. 1A) comprising one or more active components ([0023]) in an active component layer (layer comprising #140);
a passive interposer region (outside sections of interposer layer containing interposers #130) that contains no active components ([0022]); and
an interconnect layer (layer comprising pads #143) that is configured to transfer at least one of power and a signal ([0023]) from a bottom-side bump (#137, Fig. 1A) on a bottom side bump of the chip (#100) to a to a device (#120) located above the active interposer region, directly or indirectly, through a via (#134, #144) of the active interposer (#140).
Regarding Claim 13, Pietambaram discloses: The semiconductor device of claim 12,
Pietambaram further discloses:
See Fig. 1A.
wherein the active interposer region (#140) comprises a different number of layers than the passive interposer region (#130).
Regarding Claim 14, Pietambaram discloses: The semiconductor device of claim 12,
Pietambaram further discloses:
wherein the active interposer (#140) is embedded within a trench (#135) formed in the chip (#100).
Regarding Claim 15, Pietambaram discloses: The semiconductor device of claim 14 wherein:
Pietambaram further discloses:
a) contact vias (#182) to the active interposer (#140) are formed in a pattern contacts layer (portion of #132 above active interposer and/or portion of #122 above active interposer) located only in a region above the embedded active interposer (#140); or
b) another layer (portion of #132 above active interposer and passive interposer and/or portion of #122 above active interposer and passive interposer) is formed across the active interposer region (#140) and the passive interposer region (#130) into which contact vias (#182) are formed.
Regarding Claim 16, Pietambaram discloses: The semiconductor device of claim 12,
Pietambaram further discloses:
further comprising a first chiplet (#120 left, [0026], Fig. 1A) that is mounted on the chip (#100) and above the active interposer (#140) and is connected to the active interposer (#140) through a via (#182, Fig. 1B).
Regarding Claim 17, Pietambaram discloses: The semiconductor device of claim 16,
Pietambaram further discloses:
wherein the first chiplet (#120 left) partially overlaps (Fig. 1A) the active interposer region (#140).
Regarding Claim 18, Pietambaram discloses: The semiconductor device of claim 16,
Pietambaram further discloses:
See [0026]: “…the electronic package 100 may further include one or more dies 120 embedded in a mold layer 122.” Also, see alternative embodiment shown in Fig. 4A showing a top down view of an exemplary embodiment showing one device die overlapping the active interposer region.
wherein the first chiplet (#420A) fully overlaps the active interposer region (#440).
Regarding Claim 19, Pietambaram discloses: The semiconductor device of claim 16,
Pietambaram further discloses:
further comprising:
a second chiplet (#120 right, [0026], Fig. 1A) that is mounted on the chip (#100) and above the active interposer (#140); and
an interconnection (#141) that bridges between the first chiplet (#120 left) and the second chiplet (#120 right).
Regarding Claim 20, Pietambaram discloses: The semiconductor device of claim 19,
Pietambaram further discloses:
wherein the first chiplet (#120 left) and the second chiplet (#120 right) are both connected to bumps (#137) on the bottom of the chip (#100) through vias (#134).
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention.
Claims 7-8 are rejected under 35 U.S.C. 103 as being unpatentable over US 2022/0278032 A1 Pietambaram et al in view of US 2022/0189850 A1 Liff et al (herein “Liff”).
Regarding Claim 7, Pietambaram discloses: The semiconductor device of claim 1,
Pietambaram does not explicitly disclose:
wherein the first chiplet is a high bandwidth memory.
However, in analogous art, Liff teaches:
See Fig. 1 and [0032]-[0033].
wherein the first chiplet (#102) is a high bandwidth memory ([0032]).
Therefore, it would have been obvious to a person of ordinary skill in the art, before the effective filing date of the claimed invention to consider combining the teachings of Liff to the device disclosed by Pietambaram and use a high bandwidth memory device for the first chiplet (die). Pietambaram is silent/generic as to the type of dies used in the construction of the semiconductor package representing #120 in Fig. 1A. Liff teaches in [0032]-[0033] that example dies #102 may be IC dies (HBM dies), high power processing dies (CPUs GPUs), memory dies, or the like. Therefore, doing so would be a simple substitution of one known die structure for another to meet the needs of the specific device.
Regarding Claim 8, Pietambaram discloses: The semiconductor device of claim 1,
Pietambaram does not explicitly disclose:
wherein the second chiplet is a graphics processing unit.
However, in analogous art, Liff teaches:
See Fig. 1 and [0032]-[0033].
wherein the second chiplet (#102) is a graphics processing unit ([0033]).
Therefore, it would have been obvious to a person of ordinary skill in the art, before the effective filing date of the claimed invention to consider combining the teachings of Liff to the device disclosed by Pietambaram and use a GPU device for the second chiplet (die). Pietambaram is silent/generic as to the type of dies used in the construction of the semiconductor package representing #120 in Fig. 1A. Liff teaches in [0032]-[0033] that example dies #102 may be IC dies (HBM dies), high power processing dies (CPUs GPUs), memory dies, or the like. Therefore, doing so would be a simple substitution of one known die structure for another to meet the needs of the specific device.
Citation of Other Pertinent Prior Art
US 2021/0335698 A1 Cheah et al
US 11844223 B1 Mathuriya et al
US 2024/0213166 A1 You et al
US 2024/0105704 A1 Zhong et al
Conclusion
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/ANDREW VICTOR PROSTOR/Examiner, Art Unit 2812 /CHRISTINE S. KIM/Supervisory Patent Examiner, Art Unit 2812
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