DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Election/Restrictions
Claims 11-17 are withdrawn from further consideration pursuant to 37 CFR 1.142(b) as being drawn to a nonelected group, there being no allowable generic or linking claim. Election was made without traverse in the reply filed on 05/12/2026.
Claim Objections
Claims 3-6, 9, and 18-20 is/are objected to because of the following informalities:
Claim 3 recites “contacting only a sidewall” in Line L3 but should read –contacting only the sidewall --.
Claim 4 recites “a source or drain structure of the first FET device” in Lines L4-5 but should read – the source or drain structure of the first FET device--.
Claim 5 recites “a source or drain structure of the second FET device” in Line L2 but should read – the source or drain structure of the second FET device--.
Claim 6 recites “a source or drain structure of the second FET device” in Line L4 but should read – the source or drain structure of the second FET device--.
Claim 9 recites “each respective first FET device, second FET device, third FET device and fourth FET device” in Lines L1-2 but should read – each of the first FET device, the second FET device, the third FET device, and the fourth FET device --.
Claim 9 recites “epitaxially grown source or drain structure” in Lines L4-5 but should read – an epitaxially grown source or drain structure --.
Claim 9 recites “the vertical stack of NS channels” in Line L5 but should read –the vertical stack of spaced apart nanosheet (NS) channels--.
Claim 9 recites “the respective FET device” in Line L5 but should read –the each of the first FET device, the second FET device, the third FET device, and the fourth FET device--.
Claim 18 recites “the first FET device and second FET device” in Lines L5-6 but should read –the first FET device and the second FET device--.
Claim 18 recites “the backside metal contact structure” in Line L9but should read – the first backside metal contact structure --.
Claim 18 recites “portions” in Line L14, but should read –second portions--.
Claim 18 recites “each third FET device and fourth FET device” in Line L15, but should read – each of the third FET device and the fourth FET device--.
The balance of claims are objected to for being dependent upon an already objected claim.
Appropriate correction is required.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claim(s) 1-6 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Li et al. (US 20230369218 A1-Li18).
Regarding claim 1, Li18 discloses a semiconductor structure comprising:
a first dielectric material layer having a backside power rail structure (First dielectric material layer 182 having a backside power rail structure 184b-Examiner's annotated Li18 Fig 9C);
a second dielectric material layer atop the first dielectric material layer (Examiner's annotated Li18 Fig 9C-Examiner's annotated Li18 Fig 9C) and
having a first field effect transistor (FET) device (First FET with S/D 118b/122b-Examiner's annotated Li18 Fig 9C) and a second FET device (Second FET 116c with S/D 122c-Examiner's annotated Li18 Fig 9C); and
a backside metal contact structure within the second dielectric layer between the first FET device and the second FET device (Backside metal contact 110b within second dielectric layer 144 between First FET 116b and second FET 116c-Examiner's annotated Li18 Fig 9C),
the backside metal contact structure having
a first portion contacting the backside power rail structure (First portion 170b of Backside metal contact 170b/110b contacting backside power rail 184/188-Examiner's annotated Li18 Fig 9C) and
a second via portion electrically contacting only a sidewall of a source or drain structure of the first FET device (Second portion 110b of Backside metal contact 170b/110b electrically contacting S/D 122b of First FET 116b-Examiner's annotated Li18 Fig 9C).
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Regarding claim 2, Li18 discloses all the elements of claim 1, as noted above.
Li18 further discloses a semiconductor structure
wherein the backside metal contact structure comprises
an insulating via structure between the first FET device and the second FET device (Insulating via structure/ portion of Second dielectric material layer 144 between first FET 116b and second FET 116c, contacting only a sidewall of 122c-Examiner's annotated Li18 Fig 9C),
the insulating via structure contacting only a sidewall of a source or drain structure of the second FET device (Insulating via structure/ portion of Second dielectric material layer 144 between first FET and second FET, contacting only a sidewall of 122c-Examiner's annotated Li18 Fig 9C).
Regarding claim 3, Li18 discloses all the elements of claim 1, as noted above.
Li18 further discloses a semiconductor structure
wherein the first portion of the backside metal contact structure contacting the backside power rail structure is of a first width (First portion 170b contacting backside power rail 184b, having a first width-Examiner's annotated Li18 Fig 9C) and
the second via portion of the backside metal contact structure contacting only a sidewall of the source or drain of the first FET device is of a second width (Second portion 110b contacting S/D 122b of First FET, having a second width-Examiner's annotated Li18 Fig 9C),
the first width being greater than the second width (the first width indicated by a horizontal line being greater than second width indicated by a second horizontal line-Examiner's annotated Li18 Fig 9C).
Regarding claim 4, Li18 discloses all the elements of claim 2, as noted above.
Li18 further discloses a semiconductor structure
wherein the backside metal contact structure further comprises:
a third top portion in contact with the second via portion (Third portion 110b of Backside metal contact 170b/110b in contact with Second portion-Examiner's annotated Li18 Fig 9C),
the third top portion of the backside metal contact structure in contact with a source or drain structure of the first FET device (Third portion 110b of Backside metal contact 170b/110b in contact with S/D 122b of First FET 116b -Examiner's annotated Li18 Fig 9C).
Regarding claim 5, Li18 discloses all the elements of claim 4, as noted above.
Li18 further discloses a semiconductor structure comprising
a separate isolated backside metal contact structure contacting a source or drain structure of the second FET device (Separate isolated backside metal contact structure 170c/110a/110c contacting S/D 122c of Second FET 116c-Examiner's annotated Li18 Fig 9C).
Regarding claim 6, Li18 discloses all the elements of claim 5, as noted above.
Li18 further discloses a semiconductor structure comprising
a BEOL metallization level atop the second dielectric material layer (BEOL metallization level 160/162 atop Second dielectric material layer 144-Examiner's annotated Li18 Fig 9C); and
a conductive via contact structure atop (Conductive via 154 atop separate isolated backside metal structure 170c/110a/110c-Examiner's annotated Li18 Fig 9C) and
electrically connecting the separate isolated backside metal contact structure (Conductive via 154 atop and electrically connecting separate isolated backside metal structure 170c/110a/110c-Examiner's annotated Li18 Fig 9C)
contacting a source or drain of the second FET device to a further metal structure within the BEOL metallization level (Conductive via 154 atop and electrically connecting separate isolated backside metal structure 170c/110a/110c, contacting s/d 122c of Second FET to a further metal structure 160 within the BEOL metallization level 160/162 atop Second dielectric material layer 144-Examiner's annotated Li18 Fig 9C).
Claim(s) 1, 8-10 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Xie et al. (US 20230154783 A1-Xie83).
Regarding claim 1, Xie83 discloses a semiconductor structure comprising:
a first dielectric material layer having a backside power rail structure (First dielectric material layer 110 having a backside power rail structure 158-Examiner's annotated Xie83 Fig 11);
a second dielectric material layer atop the first dielectric material layer (Second dielectric material layer 116 atop First dielectric material layer 110-Examiner's annotated Li18 Fig 9C-Examiner's annotated Xie83 Fig 11) and
having a first field effect transistor (FET) device (First FET 106a with S/D 138-Examiner's annotated Xie83 Fig 11, Fig 4 ) and a second FET device (Second FET 106b with S/D 138-Examiner's annotated Xie83 Fig 11, Fig 4); and
a backside metal contact structure within the second dielectric layer between the first FET device and the second FET device (Backside metal contact 142a within second dielectric layer 116 between First FET 106a and second FET 104b-Examiner's annotated Xie83 Fig 11),
the backside metal contact structure (142a-Examiner's annotated Xie83 Fig 11) having
a first portion contacting the backside power rail structure (First portion of Backside metal contact 142a contacting backside power rail 158-Examiner's annotated Xie83 Fig 11) and
a second via portion electrically contacting only a sidewall of a source or drain structure of the first FET device (Second portion of Backside metal contact 142a electrically contacting S/D 138 of First FET 106a-Examiner's annotated Xie83 Fig 11).
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Regarding claim 8, Xie83 discloses all the elements of claim 1, as noted above.
Xie83 further discloses a semiconductor structure comprising:
a further backside power rail structure in the first dielectric material layer (Further Backside power rail structure 158 in First dielectric material layer 110-Examiner's annotated Xie83 Fig 11);
a third FET device in the second dielectric material layer (Third FET 106c with S/D 138 in Second dielectric material layer 116-Examiner's annotated Xie83 Fig 11) and
a fourth FET device adjacent the third FET device in the second dielectric material layer (Fourth FET 106d with S/D 138 adjacent to Third FET 106c in Second dielectric material layer 116-Examiner's annotated Xie83 Fig 11); and
a further backside metal contact structure within the second dielectric layer between the third FET device and the fourth FET device (Further Backside metal contact 142a within second dielectric layer 116 between Third FET 106c and Fourth FET 106d-Examiner's annotated Xie83 Fig 11),
the further backside metal contact structure electrically contacting the further backside power rail structure (Further Backside metal contact 142a within second dielectric layer 116 between Third FET 106c and Fourth FET 106d, electrically contacting backside power rail 158-Examiner's annotated Xie83 Fig 11) and
electrically contacting both sidewalls of the source or drain structure of the third FET device and the fourth FET device facing each other (Further Backside metal contact 142a within second dielectric layer 116 between Third FET 106c and Fourth FET 106d, electrically contacting backside power rail 158, electrically contacting both sidewalls of s/d 138-Examiner's annotated Xie83 Fig 11).
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Regarding claim 9, Xie83 discloses all the elements of claim 8, as noted above.
Xie83 further discloses a semiconductor structure comprising:
wherein each respective first FET device, second FET device, third FET device and fourth FET device is a gate-all-around (GAA) field effect transistor device (First FET 106a and second FET 106b being NFET, and the third FET device and fourth FET device are of a second FET type, so all being GAA FET-[0028] L1-10, Fig 2),
each having a vertical stack of spaced apart nanosheet (NS) channels (Each FET 106 having vertical stack of spaced apart nanosheets-Fig 1, [0034] L1-7)
surrounded by a respective gate structure (surrounded by gate structure 130-Fig 5B) and
epitaxially grown source or drain structure contacting one end of the vertical stack of NS channels of the respective FET device ([0034] L1-7).
Regarding claim 10, Xie83 discloses all the elements of claim 8, as noted above.
Xie83 further discloses a semiconductor structure comprising:
wherein the first FET and second FET devices are of a first FET type (First FET 106a and second FET 106b being NFET so being of a first FET type-[0028] L1-10) and
the third FET device and fourth FET device are of a second FET type (Third FET 106c and fourth FET 106c being PFET so being of a second FET type-[0028] L1-10).
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 7 is/are rejected under 35 U.S.C. 103 as being unpatentable over Li et al. (US 20230369218 A1-Li18) in view of Xie et al. (US 20230154783 A1-Xie83).
Regarding claim 7, Li18 discloses all the elements of claim 2, as noted above.
Li18 does not disclose a semiconductor structure
an asymmetric source or drain sidewall spacer formed on an opposite side of the source/drain structure of the first FET device
that is contacting the second via portion of the backside metal contact structure; and
an asymmetric source or drain sidewall spacer formed on an opposite side of the source/drain structure of the second FET device
that is contacting the insulating via structure.
Xie83 teaches a semiconductor structure
an asymmetric source or drain sidewall spacer formed on an opposite side of the source/drain structure of the first FET device (Asymmetric S/D 138 sidewall Spacer 132/116 formed on an opposite side of S/D structure 138 of First FET 106a with S/D 138, contacting the second via portion 142a-Examiner's annotated Xie83 Fig 11 Zoom-in)
that is contacting the second via portion of the backside metal contact structure (Asymmetric S/D 138 sidewall Spacer 132/116 formed on an opposite side of S/D structure 138 of First FET 106a with S/D 138, contacting the second via portion 142a-Examiner's annotated Xie83 Fig 11 Zoom-in); and
an asymmetric source or drain sidewall spacer formed on an opposite side of the source/drain structure of the second FET device (Asymmetric S/D 138 sidewall Spacer 132 formed on an opposite side of S/D structure 138 of Second FET 106b with S/D 138, contacting Insulating via structure/ portion of Second dielectric material layer 116-Examiner's annotated Xie83 Fig 11 Zoom-in)
that is contacting the insulating via structure (Asymmetric S/D 138 sidewall Spacer 132 formed on an opposite side of S/D structure 138 of Second FET 106b with S/D 138, contacting Insulating via structure/ portion of Second dielectric material layer 116-Examiner's annotated Xie83 Fig 11 Zoom-in).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the semiconductor structure of Xie83, as taught by Smith06 for the purpose of lower resistance through the power rail without driving any negative impact to either via resistance or capacitance in the BEOL.
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Claim(s) 18-19 is/are rejected under 35 U.S.C. 103 as being unpatentable over Xie et al. (US 20230154783 A1-Xie83) in view of Smith et al. (US 20210098306 A1-Smith06).
Regarding claim 18, Xie83 discloses a semiconductor structure comprising:
a first dielectric material layer having a first backside power rail structure (First/ Left Backside power rail structure 158 in First dielectric material layer 110-Examiner's annotated Xie83 Fig 11 BIS) and
a second backside power rail structure (Second/Right Backside power rail structure 158 in First dielectric material layer 110-Examiner's annotated Xie83 Fig 11 BIS);
a second dielectric material layer atop the first dielectric material layer (Second dielectric material layer 116 atop First dielectric material layer 110-Examiner's annotated Li18 Fig 9C-Examiner's annotated Xie83 Fig 11 BIS) and having
a first field effect transistor (FET) device (First FET 106a with S/D 138-Examiner's annotated Xie83 Fig 11 BIS, Fig 4) and
a second FET device (Second FET 106b with S/D 138-Examiner's annotated Xie83 Fig 11 BIS, Fig 4),
the first FET device and second FET device of a first conductivity type (First FET 106a and second FET 106b being NFET so being of a first conductivity type-[0028] L1-10),
the second dielectric material layer having
a third FET device and a fourth FET device of a second conductivity type (Third FET 106c and fourth FET 106c being PFET so being of a second conductivity type-[0028] L1-10); and
a first backside metal contact structure within the second dielectric layer (First/Left Backside metal contact 142a within second dielectric layer 116-Examiner's annotated Xie83 Fig 11 BIS)
between the first FET device and the second FET device (First/Left Backside metal contact 142a within second dielectric layer 116 between First FET 106a and second FET 104b-Examiner's annotated Xie83 Fig 11 BIS),
the backside metal contact structure having
a first portion contacting the first backside power rail structure (First portion of First/Left Backside metal contact 142a contacting First/ Left Backside power rail structure 158-Examiner's annotated Xie83 Fig 11 BIS) and
a second via portion electrically contacting only a sidewall of a source or drain structure of the first FET device (Second portion of First/Left Backside metal contact 142a electrically contacting S/D 138 of First FET 106a-Examiner's annotated Xie83 Fig 11 BIS); and
a second backside metal contact structure within the second dielectric layer (Second/Right Backside metal contact 142a within second dielectric layer 116-Examiner's annotated Xie83 Fig 11 BIS)
between the third FET device and the fourth FET device (Second/Right Backside metal contact 142a within second dielectric layer 116, between Third FET 106c and Fourth FET 106d-Examiner's annotated Xie83 Fig 11 BIS),
the second backside metal contact structure having
portions contacting the second backside power rail structure (Portions of Second/Right Backside metal contact 142a contacting Second/Right Backside power rail structure 158-Examiner's annotated Xie83 Fig 11 BIS).
Xie83 does not disclose a semiconductor structure wherein
the second backside metal contact structure having
portions wholly contacting sidewalls of both a source or drain structure of each third FET device and fourth FET device.
Smith06 teaches a semiconductor structure wherein
the second backside metal contact structure having
portions wholly contacting sidewalls of both a source or drain structure of each third FET device and fourth FET device (Second portions of Second/Right Backside metal contact 228c wholly contacting D 212c of Third FET and D 224c of Fourth FET-Examiner's annotated Smith06 Fig 2).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the semiconductor structure of Xie83, as taught by Smith06 for the purpose of creating an output terminal of an inverter (Smith06: [0108]).
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Regarding claim 19, Xie83 and Smith06 combination discloses all the elements of claim 18, as noted above.
Xie83 further discloses a semiconductor structure comprising:
wherein the first backside metal contact structure comprises
an insulating via structure between the first FET device and the second FET device (Insulating via structure/ portion of Second dielectric material layer 116 between first FET and second FET-Examiner's annotated Xie83 Fig 11 BIS),
the insulating via structure contacting only a sidewall of the source or drain structure of the second FET device (Insulating via structure/ portion of Second dielectric material layer 116 between first FET and second FET, contacting only a sidewall of Second S/D 138-Examiner's annotated Xie83 Fig 11 BIS).
Claim(s) 20 is/are rejected under 35 U.S.C. 103 as being unpatentable over Xie et al. (US 20230154783 A1-Xie83) in view of Smith et al. (US 20210098306 A1-Smith06), and further in view of Li et al. (US 20230369218 A1-Li18).
Regarding claim 20, Xie83 and Smith06 combination discloses all the elements of claim 18, as noted above.
Xie83 further discloses a semiconductor structure comprising:
wherein the first portion of the first backside metal contact structure contacting the backside power rail structure is of a first width (First portion of First/Left Backside metal contact 142a contacting First/ Left Backside power rail structure 158, having a first width-Examiner's annotated Xie83 Fig 11 BIS) and
the second via portion of the first backside metal contact structure contacting only a sidewall of the source or drain of the first FET device is of a second width (Second portion of First/Left Backside metal contact 142a electrically contacting S/D 138 of First FET 106a, having a second width-Examiner's annotated Xie83 Fig 11 BIS).
Xie83 and Smith06 combination does not teach a semiconductor structure wherein
the first width being greater than the second width.
Li18 teaches a semiconductor structure wherein
the first width being greater than the second width (the first width indicated by a horizontal line being greater than second width indicated by a second horizontal line-Examiner's annotated Li18 Fig 9C).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the semiconductor structure of Xie83 in view of Smith06, as taught by Li18 for the purpose of improving the routability for field-effect transistor (FET) (Li18: [0041]).
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Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
Hong et al. (US 20240079330 A1-Hong30) discloses a semiconductor structure comprising a backside power rail structure 172, a backside metal contact structure 148 having a first portion contacting the backside power rail 172 (Fig 2A) and a second via portion electrically contacting only a sidewall of a source or drain structure of the first FET device 126-1 (Fig 4).
Xie et al. (US 20230139929 A1-Xie29) discloses a semiconductor structure comprising a backside power rail structure 16, a backside metal contact structure 46B having a first portion contacting the backside power rail 16 (Fig 12B) and a second via portion electrically contacting only a sidewall of a source or drain structure of the first/Left FET device 26 (Fig 12B).
Any inquiry concerning this communication or earlier communications from the examiner should be directed to NATHALIE R FAYETTE whose telephone number is (571)272-1220. The examiner can normally be reached Monday-Friday 8:30 am-6pm ET.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Christine Kim can be reached at (571) 272-8458. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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NATHALIE R. FAYETTE
Examiner
Art Unit 2812
/NATHALIE R FAYETTE/Examiner, Art Unit 2812 06/22/2026
/CHRISTINE S. KIM/Supervisory Patent Examiner, Art Unit 2812
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