DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claim(s) 1, 3, 9 and 11 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Imam et al. (USPAPN 2019/0326280).
With respect to claim 1, Imam et al. discloses, in Figs. 6, 9 and 18), an electronic device (device of Fig. 6 additionally construction details of the transistors disclosed in Figs. 9 and 18), comprising:
a gallium nitride (GaN) substrate (substrate of 204, 203 and 200 with 206 of Fig. 18 which discloses the construction of Q1 and Q2 of Fig. 6) comprising a GaN-based top layer (204/203, see paragraph 0050) attached to a silicon-based bottom layer (substrate layer 200/206 which is silicon based, see paragraph 0050);
a bidirectional switch formed on the GaN-based top layer (Q1 with Q2) and including a first source node (S1), a second source node (S2) and a common drain node (common drain of Q1 with Q2);
a first transistor formed on the GaN-based top layer (Q3, both Q3 and Q4 are monolithically integrated with switch circuit 100, i.e., Q1 and Q2, and are made of GaN, see paragraph 0052 and are thus formed on the GaN top layer), the first transistor having a first source terminal (S3 at SUB), a first drain terminal (D3 to Vss1) and a first gate terminal (G3), the first source terminal connected directly to the silicon-based bottom layer (S3 is directly connected to the substrate/SUB), the first drain terminal connected to the first source node (at the Vss1 node) and the first gate terminal coupled to a first bias generator circuit (GD2);
a second transistor formed on the GaN-based top layer(e.g., Q4, both Q3 and Q4 are monolithically integrated with switch circuit 100, i.e., Q1 and Q2, and are made of GaN, see paragraph 0052 and are thus formed on the GaN top layer), the second transistor having a second source terminal (S4), a second drain terminal (D4) and a second gate terminal (G4), the second source terminal connected directly to the silicon-based bottom layer (S4 is directly connected to SUB), the second drain terminal connected to the second source node (at Vss2) and the second gate terminal coupled to a second bias generator circuit (GD1); and
wherein the first bias generator circuit and the first transistor are arranged to couple the first source node to the silicon-based bottom layer (when Q3 is turned on S1 and SUB will be connected via the source to drain conduction path of Q3) in response to a voltage at the second source node being at a voltage that is higher than a voltage of the silicon-based bottom layer (Q3 is turned on when the voltage at its gate, i.e., Vss2 at the second source node via GD2, is larger than its source voltage, i.e., the substrate voltage/silicon bottom layer, by the level set by the threshold voltage of Q3 and the voltage drop of GD2).
With respect to claim 3, the electronic device of claim 1, wherein the second bias generator circuit and the second transistor are arranged to couple the second source node to the silicon-based bottom layer (Q4 will connect Vss2 to S4/SUB when Q4 is turned on) in response to a voltage at the first source node being at a voltage that is higher than a voltage of the silicon-based bottom layer (Q4 is turned on when the voltage at its gate, i.e., Vss1 at the first source node via GD2, is larger than its source voltage, i.e., the substrate voltage/silicon bottom layer, by the level set by the threshold voltage of Q4 and the voltage drop of GD1).
Claims 9 and 11 are rejected for the essentially the same reasons as claims 1 and 3.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 6-7 and 14-15 is/are rejected under 35 U.S.C. 103 as being unpatentable over Imam et al. (USPAPN 2019/0326280) in view of Adachi (USPN 10,296,033).
With respect to claims 6 and 7, Imam et al. discloses that the bias generators may be FET devices (see paragraph 0032). Ostensibly the FET devices will be either one of an enhancement mode or a depletion mode transistor. However, Imam et al. fails to explicitly disclose the operation mode (either enhanced or depleted) of the transistors. Thus, Imam et al. fails to disclose, with respect to claim 6, “wherein the first and second bias generator circuits comprise depletion-mode field effect transistors (FETs), and with respect to claim 7, “wherein the first and second bias generator circuits comprise enhancement-mode field effect transistors (FETs).”
However, the devices of Imam et al. are merely known switch transistors in a substrate switching circuit of a bidirectional switch. It is old and well-known that generic switching devices of a substrate switching device of a bidirectional switch may be replaced with either depletion mode transistors (i.e., JFETs) or enhancement mode transistors (i.e., MOSFETs), since such switching devices are art recognized equivalents. This is further evidenced in Col. 22 lines 1-8 of Adachi et al.
It would have been obvious to one of ordinary skill in the art to construct the generic switch circuitry of Imam et al. with either depletion mode transistors (i.e., JFETs) or enhancement mode transistors (i.e., MOSFETs) for the purpose of having specific switched devices capable of operating as required. One would have been motivated to do so according to the types of transistors and or circuit layout available at the time of construction of the circuit.
Claims 14 and 15 are rejected for similar reasons and claims 6 and 7.
Claim(s) 17-18 is/are rejected under 35 U.S.C. 103 as being unpatentable over Imam et al. (USPAPN 2019/0326280) in view of Dosho et al (USPN 5,751,142).
With respect to claim 17, a method of forming a circuit (method of forming the circuit of Figs. 6 and 18), the method comprising:
forming a semiconductor substrate (forming the subtracted of 204, 203 and 206 of Fig. 18, see also Fig. 6);
forming a bidirectional transistor on the semiconductor substrate (forming Q1 with Q2 on 203/204 which is on 200/206), the bidirectional transistor including a first source node (S1), a second source node (S2) and a common drain node;
forming a first transistor on the semiconductor substrate (Q3, which is monolithically integrated with Q1 and Q2 and thus on the same substrate, see paragraph 0052), the first transistor having a first source terminal (S3), a first drain terminal (D3) and a first gate terminal (G3), the first source terminal connected directly to the semiconductor substrate (S3 directly connected to SUB/substrate layer), and the first drain terminal connected to the first source node (at Vss1 node);
forming a second transistor on the semiconductor substrate (Q4 which is monolithically integrated with Q1 and Q2 and thus on the same substrate, see paragraph 0052), the second transistor having a second source terminal (S4), a second drain terminal (D4) and a second gate terminal (G4), the second source terminal connected directly to the semiconductor substrate (S4 directly connected to SUB/substrate layer), the second drain terminal connected to the second source node (at Vss2 node); and
forming a third transistor having a third source terminal, a third drain terminal and a third gate terminal (Imam et al. discloses GD2 being constructed from a third diode connected FET, see paragraph 0032. Thus, one connected as claimed GD2 will have a gate, source and drain), a current terminal directly coupled to the second source node (current terminal, i.e., one of the source and drain, of the FET that constructs the cathode of diode GD2 connected to Vss2) and an additional current terminal directly coupled to the first gate terminal (other current terminal, i.e., other one of the source and drain, of the FET that constructs the anode of diode GD2 connected to G3); and
forming a fourth transistor having a fourth source terminal, a fourth drain terminal and a fourth gate terminal, the fourth drain terminal directly coupled to the first source node(current terminal, i.e., one of the source and drain, of the FET that constructs the cathode of diode GD1 connected to Vss1) and an additional terminal directly coupled to the second gate terminal (other current terminal, i.e., other one of the source and drain, of the FET that constructs the anode of diode GD1 connected to G4).
Imam et al. fails to explicitly disclose how the diode connected transistors of GD1 and GD2 are constructed. Imam et al. fails to explicitly disclose that the cathode of the FET of GD1 being the drain terminal of the FET, that the anode of the FET of GD1 being the source terminal of the FET, the cathode of the FET of GD2 being the drain terminal of the FET, that the anode of the FET of GD2 being the source terminal of the FET.
Thus, Imam et al. fails to explicitly disclose “the third drain terminal directly coupled to the second source node and the third source terminal directly coupled to the first gate terminal” and “the fourth drain terminal directly coupled to the first source node and the fourth source terminal directly coupled to the second gate terminal” as recited in claim 17.
Nevertheless, it is old and well-known to construct a diode connected FET transistor such that the cathode of the diode connected FET is formed from the drain and gate of the FET and the anode of the diode connected FET is formed from the source of the FET, since such diodes and diode connected transistors are art recognized equivalents. This is further evidenced in Figs. 6(a) and 6(e) of Dosho et al. which discloses that the source of a diode connected PMOSFET (Fig. 6(a)) is equivalent to the cathode of the diode of Fig. 6(e) and that shorted drain and gate of the diode connected PMOSFET (Fig. 6(a)) is equivalent to the cathode of the diode of Fig. 6(e).
It would have been obvious to replace the generic diodes (GD1 and GD2) with the diode connected FET 28 of Fig. 6(a) of Dosho et al., since such devices are art recognized equivalents and such a replacement is suggested by Imam et al. One would have been motivated to do so according to the types of transistors and or circuit layout available at the time of construction of the circuit.
With respect to claim 18, the method of claim 17, wherein the semiconductor substrate comprises GaN (see paragraph 0052).
Claim(s) 19-20 is/are rejected under 35 U.S.C. 103 as being unpatentable over Imam et al. (USPAPN 2019/0326280) in view of Dosho et al (USPN 5,751,142) and in further view of Adachi (USPN 10,296,033).
Claims 19-20 are rejected for similar reasons as claims 6-7.
Response to Arguments
With respect to claim of domestic benefit, proper domestic benefit has been established in view of the granted petition decision mailed 7/20/2026.
With respect to the double patenting rejections. The double patenting rejections having been withdrawn in view of the terminal disclaimers that were approved on 5/26/2026.
Applicant's arguments filed 8/27/2026 have been fully considered but they are not persuasive.
The argument that “Imam at least does not disclose ‘a first bias generator circuit’ and ‘a second bias generator circuit,” as recited by claim 1” is not persuasive, since Imam discloses a first bias generator (GD2) and a second bias generator (GD1). Furthermore, the above arguments fail to comply with 37 CFR 1.111(b) because they amount to a general allegation that the claims define a patentable invention without specifically pointing out how the language of the claims patentably distinguishes them from the references.
The argument that “[t]he elements identified in the Office Action as the first bias generator circuit and the second bias generator circuit are the auxiliary diodes GD 1 and GD2, which Imam discloses as simple diodes, and which the Office Action states are of a construction that Imam fails to explicitly disclose” is not persuasive for at least three reasons.
Firstly, examiner agrees that GD1 and GD2 are simple diodes. However, Applicant fails to provide any reasoning as to why diodes connected to the gates of transistors (e.g., at G3 and G4) cannot be interpreted as “bias generators”. The above diode elements establish the gate voltages at G3 and G4. Furthermore, the above diodes at least establish a voltage drop across the diodes and thus establish a bias voltage at the gates of G3 and G4. Thus, GD1 and GD2 are considered “bias generators” due to the broadest reasonable interpretation. It is common and known in the art to use diodes to establish bias voltages at the gates of transistor devices. This is further evidenced by Mckay et al. (USPN 10,756,613) which discloses, in Fig. 4, diodes (302) that establish bias voltages for the gates of transistor 212 and 216 at gates 208 and 216 (see Col. 7 lines 23-24). It is further noted Fig. 5 further discloses the well-known interchangeability between simple diodes (302 of Fig. 4) and diode connected transistor (402 of Fig. 5), see also Col. 6 lines 58-60.
Secondly, the allegation that with respect to GD1 and GD2 “Imam discloses as simple diodes, and which the Office Action states are of a construction that Imam fails to explicitly disclose” is incorrect. Examiner never states that the Imam fails to disclose the explicit construction of the diodes. The figures clearly show that GD1 and GD2 are explicitly constructed as diode devices. Rather, the office action states that Imam suggests that the explicit diodes may be replaced with diode connected transistors and Imam fails to explicitly disclose how the diode connected transistors that replace the generic/explicit diodes GD1 and GD2 are constructed. Nevertheless, such diode connected transistors are old and well-known as evidenced by Dosho (USPN 5,751,142).
Thirdly, again Applicant merely makes false allegations and fails to provide any reasoning for the allegations. Thus, Applicant's arguments fail to comply with 37 CFR 1.111(b) because they amount to a general allegation that the claims define a patentable invention without specifically pointing out how the language of the claims patentably distinguishes them from the references.
The argument that following argument is not persuasive:
“Further, the Office Action maps the first bias generator circuit to GD2 and the second bias generator circuit to GD1 at page 10. With respect to claim 3, the Office Action states that "Q4 is turned on when the voltage at its gate, i.e., Vss1 at the first source node via GD2, is larger than its source voltage." Office Action page 11. The same element of Imam is relied upon as both the first bias generator circuit and the second bias generator circuit.”
The statement of “Vss1 at the first source node via GD2” is merely a minor typographical error. As can be seen statement in whole recites “Q4 is turned on when the voltage at its gate, i.e., Vss1 at the first source node via GD2, is larger than its source voltage, i.e., the substrate voltage/silicon bottom layer, by the level set by the threshold voltage of Q4 and the voltage drop of GD1” (Examiner’s emphasis). One of ordinary skill in the art would understand that the above reference to GD2 was intended to read GD1. This is because GD1 has already been indicated as “the second bias circuit” and “the second transistor” was already indicated as Q4. Additionally, the last portion makes clear that it is the voltage drop of GD1 (i.e., the second bias circuit) that causes the circuit to operate as claimed. Thus, not only would it be obvious upon inspection that the citation of GD2 was a minor typographical error, but the additional information within the rejection further clarifies that it is GD1, i.e., the second bias generator, which provides the required functionality to meet the claim limitations. Thus, the above arguments are not persuasive since the rejection of claim 3 indicates the proper circuitry and the functions to provides for the claimed operations.
The following arguments are not persuasive:
“The Office Action states, "Claims 9 and 11 are rejected for the essentially the same reasons as claims 1 and 3." Office Action page 11. Claim 9 recites "a semiconductor substrate," "the first source terminal connected directly to the semiconductor substrate," and "wherein the first bias generator circuit and the first transistor are arranged to couple the first source node to the semiconductor substrate in response to a voltage at the second source node being at a voltage that is higher than a voltage of the semiconductor substrate." Anticipation requires that each and every limitation be found in a single reference. (See MPEP § 2131.) Applicant respectfully requests that the Examiner identify where each limitation of claim 9 is disclosed in Imam.”
This is because claim 9 is broader than the limitations of claim 1. For instance, claim 9 does not require “a GAN substrate comprising a GaN-based top layer attached to a silicon based bottom layer”. Thus, the recitation of "a semiconductor substrate," "the first source terminal connected directly to the semiconductor substrate," and "wherein the first bias generator circuit and the first transistor are arranged to couple the first source node to the semiconductor substrate in response to a voltage at the second source node being at a voltage that is higher than a voltage of the semiconductor substrate" are included within the indicated “a GAN substrate comprising a GaN-based top layer attached to a silicon based bottom layer”. Clearly the indicated silicon based bottom layer of claim 1 is included within the substrate of claim 9. Furthermore, it is clear from the rejection of claim 9 that the “silicon-based bottom layer” was indicated as “substrate layer 200/206”. As can be seen the “silicon-based bottom layer” of claim 1 and the “semiconductor substrate” of claim 9 include the same connections to “the first source terminal” and the same operations with respect to the claimed operations of “wherein the first bias generator circuit and the first transistor are arranged to couple the first source node to the semiconductor substrate in response to a voltage at the second source node being at a voltage that is higher than a voltage of the semiconductor substrate”. Therefore, one of ordinary skill in the art can see that by disclosing the limitations of claim 1, Imam et al. discloses all of the broader recitations of claim 9.
The arguments that Adachi at least does not disclose "depletion-mode field effect transistors (FETs)," as recited by claim 6, and at least does not disclose "enhancement-mode field effect transistors (FETs)," as recited by claim 7 are not persuasive. It is inherent that a J-FET transistor is a depletion mode transistor. Furthermore, unspecified MOSFET transistor are enhancement mode devices or at least include both enhancement and depletion mode devices as required/desired. In view of Adachi it is intended to be enhancement.
That argument that “Adachi is not relied upon in the Office Action to disclose ‘a first bias generator circuit" and "a second bias generator circuit,’ as recited by claims 1 and 9” is not persuasive for at least the reasons discussed above with respect to Imam et al. It can be seen that GD2 and GD1 are the first and second bias generators.
The following arguments are not persuasive:
“Dosho at least does not disclose "the third drain terminal directly coupled to the second source node and the third source terminal directly coupled to the first gate terminal," as recited by claim 17. Dosho likewise at least does not disclose "the fourth drain terminal directly coupled to the first source node and the fourth source terminal directly coupled to the second gate terminal," as recited by claim 17. The diode element of Dosho has an anode connected to a reference voltage output terminal and a cathode connected to an offset voltage control terminal of an operational amplifier.
Combining Imam with Dosho would not have led to the claimed subject matter because Imam and Dosho, either individually or in combination, at least do not disclose or suggest "the third drain terminal directly coupled to the second source node and the third source terminal directly coupled to the first gate terminal" and "the fourth drain terminal directly coupled to the first source node and the fourth source terminal directly coupled to the second gate terminal," as recited by claim 17. Obviousness can only be established by combining or modifying the teachings of the cited references where there is some teaching, suggestion, or motivation to do so found either in the references themselves or in the knowledge generally available to one of ordinary skill in the art. (See MPEP § 2143.01.)”
This is because it is the combination of Imam et al. and Dosho that disclose all of the cited limitations. Imam et al. clearly suggests that diode connected transistors may replace the diode devices of GD2 and GD1. When GD2 and GD1 are replaced with diode connected transistor, which Dosho evidences the well-known ways to connect transistors to be equivalent to diodes, the combination will be connected and operative as claimed. Applicant merely argues that Dosho fails to provide the claimed connections. However, it is clear that the combination of Imam et al. and Dosho provides the claimed limitations. In response to applicant's arguments against the references individually, one cannot show nonobviousness by attacking references individually where the rejections are based on combinations of references. See In re Keller, 642 F.2d 413, 208 USPQ 871 (CCPA 1981); In re Merck & Co., 800 F.2d 1091, 231 USPQ 375 (Fed. Cir. 1986).
Conclusion
THIS ACTION IS MADE FINAL. Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to Thomas J. Hiltunen whose telephone number is (571)272-5525. The examiner can normally be reached 9:00AM-5:30PM EST M-F.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Menatoallah Youssef can be reached at (571)270-3684. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/THOMAS J. HILTUNEN/ Primary Examiner, Art Unit 2836
