Technology area: Semiconductors, Circuits & Optics
5 pending office actions • 4 art units • 5 examiners • 0 of 5 (0%) have an AI response strategy ready • 15 patents granted in the last 365 days
Navitas Semiconductor Limited has 5 pending office actions in Semiconductors, Circuits & Optics. The matters involve 5 distinct examiners and 4 distinct art units. STARK, JARRETT J is the busiest examiner, with 1 pending action.
The examiner count exceeds the art-unit count, showing that at least one technical unit contains multiple pending matters. Counsel should compare those matters for consistent semiconductor terminology, claim construction, and prior-art treatment, while preparing examiner-specific responses. The STARK matter is one individual assignment rather than an identified repeated examiner relationship.
Based on the USPTO statutory response window for each pending office action. 2 of the docket's apps have a known mailing date; the rest are excluded from the tile counts.
Difficulty is derived from the rejection statutes on the most recent pending office action. §101-driven and multi-statute cases are graded Hard; §112-only and obviousness-type double-patenting cases are graded Easy; everything else is Medium. "Unknown" means we have not yet parsed a statute for that office action.
| Bucket | Cases |
|---|---|
| Multi-statute (no §101) | 5 (100%) |
How the docket's pending cases split across USPTO tech-center bands.
Manual office-action response work runs about 10 hours per case. The time-saved bands below show what IP Author's prosecution pipeline typically delivers — a conservative 20% on the low end, 35% in the middle, 50% on the high end.
| Examiner | Apps on this docket | Allow rate | Interview lift |
|---|---|---|---|
| STARK, JARRETT J | 1 | 70.4% | +11.0% |
| HAIDER, WASIUL | 1 | 92.1% | +6.4% |
| HILTUNEN, THOMAS J | 1 | 81.5% | +6.0% |
| ADHIKARI DAWADI, BIPANA | 1 | 91.7% | -20.0% |
| LIAN, MANG TIN BIK | 1 | 70.4% | +26.0% |
Multi-statute / §101-driven matters, or cases in front of an examiner with an allow rate under 30%. The top 5 ordered by deadline are shown.
| App # | Title | Examiner | Due in |
|---|---|---|---|
| 17812385 | SYSTEM AND METHODS FOR SINGULATION OF GAN-ON-SILICON WAFERS | ADHIKARI DAWADI, BIPANA | 16d overdue |
| 18398556 | CIRCUITS AND METHODS FOR GENERATING BIAS VOLTAGES IN SUBSTRATE CLAMP CIRCUITS | HILTUNEN, THOMAS J | 8d |
| 18893668 | ELECTRONIC PACKAGE FOR HIGH VOLTAGE APPLICATIONS | STARK, JARRETT J | — |
| 18893587 | ELECTRONIC PACKAGE WITH INTEGRAL SEAL | HAIDER, WASIUL | — |
| 17853767 | SYSTEMS AND METHODS FOR IMPROVING WINDING LOSSES IN PLANAR TRANSFORMERS | LIAN, MANG TIN BIK | — |
Cases in front of an examiner whose interview lift is 10 percentage points or more — i.e. interviewed cases historically resolve more favorably than non-interviewed ones. The top 2 ordered by deadline are shown.
| App # | Title | Examiner | Due in |
|---|---|---|---|
| 18893668 | ELECTRONIC PACKAGE FOR HIGH VOLTAGE APPLICATIONS | STARK, JARRETT J | — |
| 17853767 | SYSTEMS AND METHODS FOR IMPROVING WINDING LOSSES IN PLANAR TRANSFORMERS | LIAN, MANG TIN BIK | — |
| Art Unit | Apps |
|---|---|
| 2898 | 2 |
| 2812 | 1 |
| 2836 | 1 |
| 2837 | 1 |
| App # | Title | Examiner | Art Unit | Statutes | Status | Due in | AI | Filed |
|---|---|---|---|---|---|---|---|---|
| 18893668 | ELECTRONIC PACKAGE FOR HIGH VOLTAGE APPLICATIONS | STARK, JARRETT J | 2898 | §102§103 | Non-Final OA | — | Pending | Sep 23, 2024 |
| 18893587 | ELECTRONIC PACKAGE WITH INTEGRAL SEAL | HAIDER, WASIUL | 2812 | §102§103 | Non-Final OA | — | Pending | Sep 23, 2024 |
| 18398556 | CIRCUITS AND METHODS FOR GENERATING BIAS VOLTAGES IN SUBSTRATE CLAMP CIRCUITS | HILTUNEN, THOMAS J | 2836 | §102§103 | Final Rejection | 8d | Pending | Dec 28, 2023 |
| 17812385 | SYSTEM AND METHODS FOR SINGULATION OF GAN-ON-SILICON WAFERS | ADHIKARI DAWADI, BIPANA | 2898 | §102§103 | Non-Final OA | 16d overdue | Pending | Jul 13, 2022 |
| 17853767 | SYSTEMS AND METHODS FOR IMPROVING WINDING LOSSES IN PLANAR TRANSFORMERS | LIAN, MANG TIN BIK | 2837 | §103§112 | Final Rejection | — | Pending | Jun 29, 2022 |
IP Author helps IP teams respond to office actions faster with AI-generated responses, examiner analytics, and prosecution intelligence.
Start Free TrialNavitas Semiconductor Limited has 5 pending office actions as of October 2026, spread across 4 art units and 5 examiners.
Jarrett J Stark has the most, with 1 of Navitas Semiconductor Limited's pending office actions.
Mostly Semiconductors, Circuits & Optics (USPTO Tech Center 2800), based on where its pending office actions are examined.
