DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
ADS
A proper domestic benefit claim must be provided in the Application Data Sheet in order to constitute a claim for domestic benefit. See 37 CFR 1.76 and 1.78.
This application makes reference to or appears to claim subject matter disclosed in Application No. 18/064,185, filed 12/9/22, Application No. 17/850,792, filed 6/27/22 and U.S. provisional Application No. 63/202,901, filed 6/29/21. If applicant desires to claim the benefit of a prior-filed application under 35 U.S.C. 119(e), 120, 121, 365(c) or 386(c), the instant application must contain, or be amended to contain, a specific reference to the prior-filed application in compliance with 37 CFR 1.78. If the application was filed before September 16, 2012, the specific reference must be included in the first sentence(s) of the specification following the title or in an application data sheet (ADS) in compliance with pre-AIA 37 CFR 1.76; if the application was filed on or after September 16, 2012, the specific reference must be included in an ADS in compliance with 37 CFR 1.76. For benefit claims under 35 U.S.C. 120, 121, 365(c), or 386(c), the reference must include the relationship (i.e., continuation, divisional, or continuation-in-part) of the applications.
If the instant application is a utility or plant application filed under 35 U.S.C. 111(a), the specific reference must be submitted during the pendency of the application and within the later of four months from the actual filing date of the application or sixteen months from the filing date of the prior application. If the application is a national stage application under 35 U.S.C. 371, the specific reference must be submitted during the pendency of the application and within the later of four months from the date on which the national stage commenced under 35 U.S.C. 371(b) or (f), four months from the date of the initial submission under 35 U.S.C. 371 to enter the national stage, or sixteen months from the filing date of the prior application. See 37 CFR 1.78(a)(4) for benefit claims under 35 U.S.C. 119(e) and 37 CFR 1.78(d)(3) for benefit claims under 35 U.S.C. 120, 121, 365(c), or 386(c). This time period is not extendable and a failure to submit the reference required by 35 U.S.C. 119(e) and/or 120, where applicable, within this time period is considered a waiver of any benefit of such prior application(s) under 35 U.S.C. 119(e), 120, 121, 365(c), and 386(c). A benefit claim filed after the required time period may be accepted if it is accompanied by a grantable petition to accept an unintentionally delayed benefit claim under 35 U.S.C. 119(e) (see 37 CFR 1.78(c)) or under 35 U.S.C. 120, 121, 365(c), or 386(c) (see 37 CFR 1.78(e)). The petition must be accompanied by (1) the reference required by 35 U.S.C. 120 or 119(e) and by 37 CFR 1.78 to the prior application (unless previously submitted), (2) the applicable petition fee under 37 CFR 1.17(m)(1) or (2), and (3) a statement that the entire delay between the date the benefit claim was due under 37 CFR 1.78 and the date the claim was filed was unintentional. The presentation of a benefit claim may result in an additional fee under 37 CFR 1.17(w)(1) or (2) being required, if the earliest filing date for which benefit is claimed under 35 U.S.C. 120, 121, 365(c), or 386(c) and 1.78(d) in the application is more than six years before the actual filing date of the application. The Director may require additional information where there is a question whether the delay was unintentional. The petition should be addressed to: Mail Stop Petition, Commissioner for Patents, P.O. Box 1450, Alexandria, Virginia 22313-1450.
If the reference to the prior application was previously submitted within the time period set forth in 37 CFR 1.78 but was not included in the location in the application required by the rule (e.g., if the reference was submitted in an oath or declaration or the application transmittal letter), and the information concerning the benefit claim was recognized by the Office as shown by its inclusion on the first filing receipt, the petition under 37 CFR 1.78 and the petition fee under 37 CFR 1.17(m)(1) or (2) are not required. Applicant is still required to submit the reference in compliance with 37 CFR 1.78 by filing an ADS in compliance with 37 CFR 1.76 with the reference (or, if the application was filed before September 16, 2012, by filing either an amendment to the first sentence(s) of the specification or an ADS in compliance with pre-AIA 37 CFR 1.76). See MPEP § 211.02.
Double Patenting
The nonstatutory double patenting rejection is based on a judicially created doctrine grounded in public policy (a policy reflected in the statute) so as to prevent the unjustified or improper timewise extension of the “right to exclude” granted by a patent and to prevent possible harassment by multiple assignees. A nonstatutory double patenting rejection is appropriate where the conflicting claims are not identical, but at least one examined application claim is not patentably distinct from the reference claim(s) because the examined application claim is either anticipated by, or would have been obvious over, the reference claim(s). See, e.g., In re Berg, 140 F.3d 1428, 46 USPQ2d 1226 (Fed. Cir. 1998); In re Goodman, 11 F.3d 1046, 29 USPQ2d 2010 (Fed. Cir. 1993); In re Longi, 759 F.2d 887, 225 USPQ 645 (Fed. Cir. 1985); In re Van Ornum, 686 F.2d 937, 214 USPQ 761 (CCPA 1982); In re Vogel, 422 F.2d 438, 164 USPQ 619 (CCPA 1970); In re Thorington, 418 F.2d 528, 163 USPQ 644 (CCPA 1969).
A timely filed terminal disclaimer in compliance with 37 CFR 1.321(c) or 1.321(d) may be used to overcome an actual or provisional rejection based on nonstatutory double patenting provided the reference application or patent either is shown to be commonly owned with the examined application, or claims an invention made as a result of activities undertaken within the scope of a joint research agreement. See MPEP § 717.02 for applications subject to examination under the first inventor to file provisions of the AIA as explained in MPEP § 2159. See MPEP § 2146 et seq. for applications not subject to examination under the first inventor to file provisions of the AIA . A terminal disclaimer must be signed in compliance with 37 CFR 1.321(b).
The filing of a terminal disclaimer by itself is not a complete reply to a nonstatutory double patenting (NSDP) rejection. A complete reply requires that the terminal disclaimer be accompanied by a reply requesting reconsideration of the prior Office action. Even where the NSDP rejection is provisional the reply must be complete. See MPEP § 804, subsection I.B.1. For a reply to a non-final Office action, see 37 CFR 1.111(a). For a reply to final Office action, see 37 CFR 1.113(c). A request for reconsideration while not provided for in 37 CFR 1.113(c) may be filed after final for consideration. See MPEP §§ 706.07(e) and 714.13.
The USPTO Internet website contains terminal disclaimer forms which may be used. Please visit www.uspto.gov/patent/patents-forms. The actual filing date of the application in which the form is filed determines what form (e.g., PTO/SB/25, PTO/SB/26, PTO/AIA /25, or PTO/AIA /26) should be used. A web-based eTerminal Disclaimer may be filled out completely online using web-screens. An eTerminal Disclaimer that meets all requirements is auto-processed and approved immediately upon submission. For more information about eTerminal Disclaimers, refer to www.uspto.gov/patents/apply/applying-online/eterminal-disclaimer.
Claims 9, 11, 14-15 and 17-20 are rejected on the ground of nonstatutory double patenting as being unpatentable over claims 8-20 of U.S. Patent No. 11,870,429 (‘429 hereinafter). Although the claims at issue are not identical, they are not patentably distinct from each other because the above claims of the instant application are essentially the same as that of the above claims of ‘429 with minor differences such as claims 8 and 17 of ‘429 requires that the “third gate” of the “third transistor” is “connected to a voltage source” and that the “fourth gate” of the “fourth transistor” is “connected to the voltage source”, whereas claims 9 and 17 of the instant application does not require the third and fourth gates being connected to the voltage source. Nevertheless it would have been obvious to remove the voltage source from the circuitry as recited in claims 8 and 17 of ‘429, since it has been held that omission of an element and its function in a combination where the remaining elements perform the same functions as before involves only routine skill in the art. In re Karlson, 136 USPQ 184. One would have been motivated to do so to simplify circuit constructions.
Additionally, ‘429 differs from the instant application since ‘429 does not explicitly state that there are “direct” connections, such as “the first source terminal connected directly to the silicon-based bottom layer”, “the second source connected directly to the silicon-based bottom layer”, “the third drain terminal directly coupled to the second source node”, “the third drain directly coupled to the first gate terminal”, “the fourth drain terminal directly coupled to the first source node”, and “the fourth source terminal directly coupled to the second gate terminal” as required in claim 1 (and similar recitation in claims 8 and 17) of the instant application. Rather, ‘429 includes the above connections, but they are merely recited as being “connected” or “coupled” without the explicit requirement of a “direct” connection or coupling. Nevertheless the terms “connected” and “coupled” are broad and include both an indirect and the direct coupling and connections. For instance, devices that are directly connected and/or coupled are inherently connected and/or coupled together. It would have been obvious to include direct connections and/or couplings within the broader recitations of connected/coupled of ‘429 since the broad recitations anticipates the more specific direct connections. It would have been obvious to make direct connections/couplings for the purpose of having the least amount of materials and/or devices to construct the circuit and fabricate the connections between devices of ‘429. One would have been motivated to do so for the purpose of simplifying circuit construction.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claim(s) 1, 3, 9 and 11 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Imam et al. (USPAPN 2019/0326280).
With respect to claim 1, Imam et al. discloses, in Figs. 6, 9 and 18), an electronic device (device of Fig. 6 additionally construction details of the transistors disclosed in Figs. 9 and 18), comprising:
a gallium nitride (GaN) substrate (substrate of 204, 203 and 200 with 206 of Fig. 18 which discloses the construction of Q1 and Q2 of Fig. 6) comprising a GaN-based top layer (204/203, see paragraph 0050) attached to a silicon-based bottom layer (substrate layer 200/206 which is silicon based, see paragraph 0050);
a bidirectional switch formed on the GaN-based top layer (Q1 with Q2) and including a first source node (S1), a second source node (S2) and a common drain node (common drain of Q1 with Q2);
a first transistor formed on the GaN-based top layer (Q3, both Q3 and Q4 are monolithically integrated with switch circuit 100, i.e., Q1 and Q2, and are made of GaN, see paragraph 0052 and are thus formed on the GaN top layer), the first transistor having a first source terminal (S3 at SUB), a first drain terminal (D3 to Vss1) and a first gate terminal (G3), the first source terminal connected directly to the silicon-based bottom layer (S3 is directly connected to the substrate/SUB), the first drain terminal connected to the first source node (at the Vss1 node) and the first gate terminal coupled to a first bias generator circuit (GD2);
a second transistor formed on the GaN-based top layer(e.g., Q4, both Q3 and Q4 are monolithically integrated with switch circuit 100, i.e., Q1 and Q2, and are made of GaN, see paragraph 0052 and are thus formed on the GaN top layer), the second transistor having a second source terminal (S4), a second drain terminal (D4) and a second gate terminal (G4), the second source terminal connected directly to the silicon-based bottom layer (S4 is directly connected to SUB), the second drain terminal connected to the second source node (at Vss2) and the second gate terminal coupled to a second bias generator circuit (GD1); and
wherein the first bias generator circuit and the first transistor are arranged to couple the first source node to the silicon-based bottom layer (when Q3 is turned on S1 and SUB will be connected via the source to drain conduction path of Q3) in response to a voltage at the second source node being at a voltage that is higher than a voltage of the silicon-based bottom layer (Q3 is turned on when the voltage at its gate, i.e., Vss2 at the second source node via GD2, is larger than its source voltage, i.e., the substrate voltage/silicon bottom layer, by the level set by the threshold voltage of Q3 and the voltage drop of GD2).
With respect to claim 3, the electronic device of claim 1, wherein the second bias generator circuit and the second transistor are arranged to couple the second source node to the silicon-based bottom layer (Q4 will connect Vss2 to S4/SUB when Q4 is turned on) in response to a voltage at the first source node being at a voltage that is higher than a voltage of the silicon-based bottom layer (Q4 is turned on when the voltage at its gate, i.e., Vss1 at the first source node via GD2, is larger than its source voltage, i.e., the substrate voltage/silicon bottom layer, by the level set by the threshold voltage of Q4 and the voltage drop of GD1).
Claims 9 and 11 are rejected for the essentially the same reasons as claims 1 and 3.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 6-7 and 14-15 is/are rejected under 35 U.S.C. 103 as being unpatentable over Imam et al. (USPAPN 2019/0326280) in view of Adachi (USPN 10,296,033).
With respect to claims 6 and 7, Imam et al. discloses that the bias generators may be FET devices (see paragraph 0032). Ostensibly the FET devices will be either one of an enhancement mode or a depletion mode transistor. However, Imam et al. fails to explicitly disclose the operation mode (either enhanced or depleted) of the transistors. Thus, Imam et al. fails to disclose, with respect to claim 6, “wherein the first and second bias generator circuits comprise depletion-mode field effect transistors (FETs), and with respect to claim 7, “wherein the first and second bias generator circuits comprise enhancement-mode field effect transistors (FETs).”
However, the devices of Imam et al. are merely known switch transistors in a substrate switching circuit of a bidirectional switch. It is old and well-known that generic switching devices of a substrate switching device of a bidirectional switch may be replaced with either depletion mode transistors (i.e., JFETs) or enhancement mode transistors (i.e., MOSFETs), since such switching devices are art recognized equivalents. This is further evidenced in Col. 22 lines 1-8 of Adachi et al.
It would have been obvious to one of ordinary skill in the art to construct the generic switch circuitry of Imam et al. with either depletion mode transistors (i.e., JFETs) or enhancement mode transistors (i.e., MOSFETs) for the purpose of having specific switched devices capable of operating as required. One would have been motivated to do so according to the types of transistors and or circuit layout available at the time of construction of the circuit.
Claims 14 and 15 are rejected for similar reasons and claims 6 and 7.
Claim(s) 17-18 is/are rejected under 35 U.S.C. 103 as being unpatentable over Imam et al. (USPAPN 2019/0326280) in view of Dosho et al (USPN 5,751,142).
With respect to claim 17, a method of forming a circuit (method of forming the circuit of Figs. 6 and 18), the method comprising:
forming a semiconductor substrate (forming the subtracted of 204, 203 and 206 of Fig. 18, see also Fig. 6);
forming a bidirectional transistor on the semiconductor substrate (forming Q1 with Q2 on 203/204 which is on 200/206), the bidirectional transistor including a first source node (S1), a second source node (S2) and a common drain node;
forming a first transistor on the semiconductor substrate (Q3, which is monolithically integrated with Q1 and Q2 and thus on the same substrate, see paragraph 0052), the first transistor having a first source terminal (S3), a first drain terminal (D3) and a first gate terminal (G3), the first source terminal connected directly to the semiconductor substrate (S3 directly connected to SUB/substrate layer), and the first drain terminal connected to the first source node (at Vss1 node);
forming a second transistor on the semiconductor substrate (Q4 which is monolithically integrated with Q1 and Q2 and thus on the same substrate, see paragraph 0052), the second transistor having a second source terminal (S4), a second drain terminal (D4) and a second gate terminal (G4), the second source terminal connected directly to the semiconductor substrate (S4 directly connected to SUB/substrate layer), the second drain terminal connected to the second source node (at Vss2 node); and
forming a third transistor having a third source terminal, a third drain terminal and a third gate terminal (Imam et al. discloses GD2 being constructed from a third diode connected FET, see paragraph 0032. Thus, one connected as claimed GD2 will have a gate, source and drain), a current terminal directly coupled to the second source node (current terminal, i.e., one of the source and drain, of the FET that constructs the cathode of diode GD2 connected to Vss2) and an additional current terminal directly coupled to the first gate terminal (other current terminal, i.e., other one of the source and drain, of the FET that constructs the anode of diode GD2 connected to G3); and
forming a fourth transistor having a fourth source terminal, a fourth drain terminal and a fourth gate terminal, the fourth drain terminal directly coupled to the first source node(current terminal, i.e., one of the source and drain, of the FET that constructs the cathode of diode GD1 connected to Vss1) and an additional terminal directly coupled to the second gate terminal (other current terminal, i.e., other one of the source and drain, of the FET that constructs the anode of diode GD1 connected to G4).
Imam et al. fails to explicitly disclose how the diode connected transistors of GD1 and GD2 are constructed. Imam et al. fails to explicitly disclose that the cathode of the FET of GD1 being the drain terminal of the FET, that the anode of the FET of GD1 being the source terminal of the FET, the cathode of the FET of GD2 being the drain terminal of the FET, that the anode of the FET of GD2 being the source terminal of the FET.
Thus, Imam et al. fails to explicitly disclose “the third drain terminal directly coupled to the second source node and the third source terminal directly coupled to the first gate terminal” and “the fourth drain terminal directly coupled to the first source node and the fourth source terminal directly coupled to the second gate terminal” as recited in claim 17.
Nevertheless, it is old and well-known to construct a diode connected FET transistor such that the cathode of the diode connected FET is formed from the drain and gate of the FET and the anode of the diode connected FET is formed from the source of the FET, since such diodes and diode connected transistors are art recognized equivalents. This is further evidenced in Figs. 6(a) and 6(e) of Dosho et al. which discloses that the source of a diode connected PMOSFET (Fig. 6(a)) is equivalent to the cathode of the diode of Fig. 6(e) and that shorted drain and gate of the diode connected PMOSFET (Fig. 6(a)) is equivalent to the cathode of the diode of Fig. 6(e).
It would have been obvious to replace the generic diodes (GD1 and GD2) with the diode connected FET 28 of Fig. 6(a) of Dosho et al., since such devices are art recognized equivalents and such a replacement is suggested by Imam et al. One would have been motivated to do so according to the types of transistors and or circuit layout available at the time of construction of the circuit.
With respect to claim 18, the method of claim 17, wherein the semiconductor substrate comprises GaN (see paragraph 0052).
Claim(s) 19-20 is/are rejected under 35 U.S.C. 103 as being unpatentable over Imam et al. (USPAPN 2019/0326280) in view of Dosho et al (USPN 5,751,142) and in further view of Adachi (USPN 10,296,033).
Claims 19-20 are rejected for similar reasons as claims 6-7.
Response to Arguments
Applicant’s arguments with respect to claim(s) 1, 3, 6-7, 9, 11, 14-15 and 17-20 have been considered but are moot because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to Thomas J. Hiltunen whose telephone number is (571)272-5525. The examiner can normally be reached 9:00AM-5:30PM EST M-F.
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/THOMAS J. HILTUNEN/ Primary Examiner, Art Unit 2836
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