Prosecution Insights
Prosecution Insights
Technology area: Semiconductors, Circuits & Optics
8 pending office actions • 4 art units • 8 examiners • 0 of 8 (0%) have an AI response strategy ready • 17 patents granted in the last 365 days
Navitas Semiconductor Limited is currently managing 8 pending office actions in the Semiconductors, Circuits & Optics technology area. These 8 actions are distributed among 8 distinct examiners, meaning that each pending case is being reviewed by a different person. This 1 to 1 ratio between actions and examiners requires a customized strategy for each application. RETEBO, METASEBIA T is the busiest examiner for the company, currently overseeing 1 pending action.
The 8 pending office actions are spread across 4 distinct art units, indicating that the company's semiconductor technology falls under the jurisdiction of 4 different specialized groups at the USPTO. With 8 distinct examiners and 4 distinct art units, the prosecution landscape is moderately diverse for a portfolio of this size. Since RETEBO, METASEBIA T only handles 1 pending action, no single examiner has a dominant role in the current portfolio. Practitioners must navigate the specific standards of 4 art units while addressing the individual feedback of 8 different examiners to advance these 8 pending matters. This decentralized structure requires careful coordination to ensure consistency across the 4 art units involved.
Based on the USPTO statutory response window for each pending office action. 2 of the docket's apps have a known mailing date; the rest are excluded from the tile counts.
Difficulty is derived from the rejection statutes on the most recent pending office action. §101-driven and multi-statute cases are graded Hard; §112-only and obviousness-type double-patenting cases are graded Easy; everything else is Medium. "Unknown" means we have not yet parsed a statute for that office action.
| Bucket | Cases |
|---|---|
| §101 only | 1 (12%) |
| Multi-statute (no §101) | 7 (88%) |
How the docket's pending cases split across USPTO tech-center bands.
Manual office-action response work runs about 10 hours per case. The time-saved bands below show what IP Author's prosecution pipeline typically delivers — a conservative 20% on the low end, 35% in the middle, 50% on the high end.
| Examiner | Apps on this docket | Allow rate | Interview lift |
|---|---|---|---|
| RETEBO, METASEBIA T | 1 | 89.5% | +5.3% |
| ALMO, KHAREEM E | 1 | 87.3% | +5.6% |
| BERHANE, ADOLF D | 1 | 88.4% | -1.8% |
| STARK, JARRETT J | 1 | 70.5% | +11.5% |
| HAIDER, WASIUL | 1 | 92.0% | +6.4% |
| HILTUNEN, THOMAS J | 1 | 81.4% | +6.1% |
| ADHIKARI DAWADI, BIPANA | 1 | 91.7% | -20.0% |
| LIAN, MANG TIN BIK | 1 | 70.4% | +26.0% |
Multi-statute / §101-driven matters, or cases in front of an examiner with an allow rate under 30%. The top 8 ordered by deadline are shown.
| App # | Title | Examiner | Due in |
|---|---|---|---|
| 17812385 | SYSTEM AND METHODS FOR SINGULATION OF GAN-ON-SILICON WAFERS | ADHIKARI DAWADI, BIPANA | 16d overdue |
| 18398556 | CIRCUITS AND METHODS FOR GENERATING BIAS VOLTAGES IN SUBSTRATE CLAMP CIRCUITS | HILTUNEN, THOMAS J | 8d |
| 19278617 | CIRCUITS AND METHODS FOR CONTROLLING A VOLTAGE OF A SEMICONDUCTOR SUBSTRATE | RETEBO, METASEBIA T | — |
| 19185090 | INTEGRATED GAN POWER DEVICES INCLUDING PFC AND QR FLYBACK CONTROLLERS | ALMO, KHAREEM E | — |
| 18922179 | SYSTEMS AND METHODS FOR AUTOMATIC DETERMINATION OF STATE OFSWITCHES IN POWER CONVERTERS | BERHANE, ADOLF D | — |
| 18893668 | ELECTRONIC PACKAGE FOR HIGH VOLTAGE APPLICATIONS | STARK, JARRETT J | — |
| 18893587 | ELECTRONIC PACKAGE WITH INTEGRAL SEAL | HAIDER, WASIUL | — |
| 17853767 | SYSTEMS AND METHODS FOR IMPROVING WINDING LOSSES IN PLANAR TRANSFORMERS | LIAN, MANG TIN BIK | — |
Cases in front of an examiner whose interview lift is 10 percentage points or more — i.e. interviewed cases historically resolve more favorably than non-interviewed ones. The top 2 ordered by deadline are shown.
| App # | Title | Examiner | Due in |
|---|---|---|---|
| 18893668 | ELECTRONIC PACKAGE FOR HIGH VOLTAGE APPLICATIONS | STARK, JARRETT J | — |
| 17853767 | SYSTEMS AND METHODS FOR IMPROVING WINDING LOSSES IN PLANAR TRANSFORMERS | LIAN, MANG TIN BIK | — |
| Art Unit | Apps |
|---|---|
| 2838 | 1 |
| 2849 | 1 |
| 2898 | 1 |
| 2837 | 1 |
| App # | Title | Examiner | Art Unit | Statutes | Status | Due in | AI | Filed |
|---|---|---|---|---|---|---|---|---|
| 19278617 | CIRCUITS AND METHODS FOR CONTROLLING A VOLTAGE OF A SEMICONDUCTOR SUBSTRATE | RETEBO, METASEBIA T | — | §102§103Other | Non-Final OA | — | Pending | Jul 23, 2025 |
| 19185090 | INTEGRATED GAN POWER DEVICES INCLUDING PFC AND QR FLYBACK CONTROLLERS | ALMO, KHAREEM E | — | §102§103 | Non-Final OA | — | Pending | Apr 21, 2025 |
| 18922179 | SYSTEMS AND METHODS FOR AUTOMATIC DETERMINATION OF STATE OFSWITCHES IN POWER CONVERTERS | BERHANE, ADOLF D | 2838 | §101 | Non-Final OA | — | Pending | Oct 21, 2024 |
| 18893668 | ELECTRONIC PACKAGE FOR HIGH VOLTAGE APPLICATIONS | STARK, JARRETT J | — | §102§103 | Non-Final OA | — | Pending | Sep 23, 2024 |
| 18893587 | ELECTRONIC PACKAGE WITH INTEGRAL SEAL | HAIDER, WASIUL | — | §102§103 | Non-Final OA | — | Pending | Sep 23, 2024 |
| 18398556 | CIRCUITS AND METHODS FOR GENERATING BIAS VOLTAGES IN SUBSTRATE CLAMP CIRCUITS | HILTUNEN, THOMAS J | 2849 | §102§103Other | Non-Final OA | 8d | Pending | Dec 28, 2023 |
| 17812385 | SYSTEM AND METHODS FOR SINGULATION OF GAN-ON-SILICON WAFERS | ADHIKARI DAWADI, BIPANA | 2898 | §102§103 | Non-Final OA | 16d overdue | Pending | Jul 13, 2022 |
| 17853767 | SYSTEMS AND METHODS FOR IMPROVING WINDING LOSSES IN PLANAR TRANSFORMERS | LIAN, MANG TIN BIK | 2837 | §103§112 | Final Rejection | — | Pending | Jun 29, 2022 |
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