Notice of Pre-AIA or AIA Status The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA. Claim Rejections - 35 USC § 112 The following is a quotation of 35 U.S.C. 112(d): (d) REFERENCE IN DEPENDENT FORMS.—Subject to subsection (e), a claim in dependent form shall contain a reference to a claim previously set forth and then specify a further limitation of the subject matter claimed. A claim in dependent form shall be construed to incorporate by reference all the limitations of the claim to which it refers. The following is a quotation of pre-AIA 35 U.S.C. 112, fourth paragraph: Subject to the following paragraph [i.e., the fifth paragraph of pre-AIA 35 U.S.C. 112], a claim in dependent form shall contain a reference to a claim previously set forth and then specify a further limitation of the subject matter claimed. A claim in dependent form shall be construed to incorporate by reference all the limitations of the claim to which it refers. Claims 15-17 rejected under 35 U.S.C. 112(d) or pre-AIA 35 U.S.C. 112, 4th paragraph, as being of improper dependent form for failing to further limit the subject matter of the claim upon which it depends, or for failing to include all the limitations of the claim upon which it depends. The preamble to claim 15 recites the limitation “ The apparatus of Claim 15, wherein …” and so the claim depends upon itself. Applicant may cancel the claim(s), amend the claim(s) to place the claim(s) in proper dependent form, rewrite the claim(s) in independent form, or present a sufficient showing that the dependent claim(s) complies with the statutory requirements. Claims 16-17 are rejected under 35 U.S.C. 112(d) as being dependent upon a claim rejected under 35 U.S.C. 112(d) . Allowable Subject Matter Claims 1-14 and 18-20 are allowed. The following is a statement of reasons for the indication of allowable subject matter: Regarding claim 1 and its dependent claims . The closest prior art ( US5239447A , US20170018485A1 , US20180145060A1 ) teaches a n apparatus comprising: a plurality of vertically oriented semiconductor memory slices, each semiconductor memory slice having one or more memory elements disposed thereon for storing data ( Cotues fig. 4 electronic device stack 30 comprised of plurality of electronic devices 40 , and par. 3 teaches that “[t] he most dense packaging configuration for semiconductor chips, in particular for memory chips, such as DRAMS, SRAMS, Flash Eproms and the like, may be obtained through the construction of a solid cube of semiconductor chips ” as shown in fig. 4 ) ; a logic chip disposed on top of the stack and oriented perpendicular to the plurality of vertically oriented semiconductor memory slices and one or more vertically oriented non- semiconductor passive slices, the logic chip having circuitry configured to process data from a semiconductor memory slice ( Appelt fig. 5 teaches a logic semiconductor die 621 disposed on top of and in electrical contact with the memory stack of semiconductor dies 12/22/32/42 ). However, the closest prior art does not teach in combination with the other claimed elements one or more vertically oriented passive slices having a conductive wire element disposed thereon for delivering power signals from a power source, the plurality of vertically oriented semiconductor memory slices and one or more vertically oriented passive slices forming a stack . wherein the wiring element delivers power signals to said logic chip circuitry . Additionally, the closest prior art does not teach the above in combination with the further limitations of dependent claims. Examiner notes that while there are embodiments within the prior art, see Cotues fig. 4 and Appelt fig. 5 , that teach vertically oriented stacked dies with a controlling logic die above and a dummy die for structural support only , examiner's search of the prior art did not find an embodiment nor any motivation to combine embodiments to produce one or more vertically oriented passive slices having a conductive wire element disposed thereon for delivering power signals from a power source wherein the wiring element delivers power signals to logic chip circuitry in addition with the other limitations of the independent claim. Regarding claim 14 and its dependent claims . The closest prior art ( US5239447A , US20170018485A1 , US20180145060A1 ) teaches a n apparatus comprising: a stacked structure comprising a plurality of vertically oriented semiconductor memory slices, each semiconductor memory slice having one or more memory elements disposed thereon for storing data ( Cotues fig. 4 electronic device stack 30 comprised of plurality of electronic devices 40, and par. 3 teaches that “[t]he most dense packaging configuration for semiconductor chips, in particular for memory chips, such as DRAMS, SRAMS, Flash Eproms and the like, may be obtained through the construction of a solid cube of semiconductor chips” as shown in fig. 4) ; and a logic chip disposed on top of the voltage step down chip and in electrical communication therewith and having circuitry configured to process data from a semiconductor memory slice ( Appelt fig. 5 teaches a logic semiconductor die 621 disposed on top of and in electrical contact with the memory stack of semiconductor dies 12/22/32/42) . However, the closest prior art does not teach in combination with the other claimed elements a plurality of vertically oriented passive slices having a conductive wire element disposed thereon for delivering power signals from a power source ; a voltage step down chip disposed on top of the stack and oriented perpendicular to the plurality of vertically oriented semiconductor memory slices and vertically oriented non- semiconductor passive slices for modifying one or more of: a voltage level, a current level or both a voltage and current level of a power signal received via said conductive wire element signal . wherein the wiring element delivers modified power signals to said logic chip circuitry Additionally, the closest prior art does not teach the above in combination with the further limitations of dependent claims. Examiner notes that while there are embodiments within the prior art, see Cotues fig. 4 and Appelt fig. 5 , that teach vertically oriented stacked dies with a controlling logic die above and a dummy die for structural support only , examiner's search of the prior art did not find an embodiment nor any motivation to combine embodiments to produce one or more vertically oriented passive slices having a conductive wire element disposed thereon for delivering power signals from a power source wherein the wiring element delivers power signals to logic chip circuitry in addition with the other limitations of the independent claim. Regarding claim 19 and its dependent claims . The closest prior art ( US5239447A , US20170018485A1 , US20180145060A1 ) teaches a method of forming a stacked memory structure comprising: providing one or more active or passive substrates having a memory die formed thereon Cotues fig. 4 plurality of electronic devices 40, and par. 3 teaches that “[t]he most dense packaging configuration for semiconductor chips, in particular for memory chips, such as DRAMS, SRAMS, Flash Eproms and the like, may be obtained through the construction of a solid cube of semiconductor chips” as shown in fig. 4 ) ; stacking an arrangement of said active or passive substrates having a memory die thereon ( Cotues fig. 4 electronic device stack 30 comprised of plurality of electronic devices 40 ) ; bonding said stacked arrangement of substrates and dies by hybrid bonding or thermal compression bonding ( Cot u es pg. 11 teaches “ bonding means such as by solder thermocompression bonding ”) ; planarizing a lateral surface of stacked dies ( Appelt par. 115 teaches “[p] lanarization steps may be performed to expose the die pads 124 ”) ; forming under-bump metallization on said planarized lateral surface ( Cotues fig. 4 solder balls 48) ; bonding said stacked bonded stacked arrangement of substrates and dies to a substrate; and dispensing an underfill material for packaging said stacked memory structure ( Appelt fig. 5 encapsulant 44) . However, the closest prior art does not teach in combination with the other claimed elements providing one or more passive substrates having a wire element formed thereon, said wire element extending from a bottom edge to a top edge of said passive substrate for delivering power sign als. stacking an arrangement of said active or passive substrates having a memory die thereon and passive substrates having a wire element formed thereon Additionally, the closest prior art does not teach the above in combination with the further limitations of dependent claims. Examiner notes that while there are embodiments within the prior art, see Cotues fig. 4 and Appelt fig. 5 , that teach vertically oriented stacked dies with a controlling logic die above and a dummy die for structural support only , examiner's search of the prior art did not find an embodiment nor any motivation to combine embodiments to produce one or more vertically oriented passive slices having a conductive wire element disposed thereon for delivering power signals from a power source wherein the wiring element delivers power signals to logic chip circuitry in addition with the other limitations of the independent claim. Conclusion Any inquiry concerning this communication or earlier communications from the examiner should be directed to FILLIN "Examiner name" \* MERGEFORMAT COLE LEON LINDSEY whose telephone number is FILLIN "Phone number" \* MERGEFORMAT (571)272-4028 . The examiner can normally be reached FILLIN "Work Schedule?" \* MERGEFORMAT Monday - Friday, 8:00 a.m. - 5:00 p.m. . Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, FILLIN "SPE Name?" \* MERGEFORMAT Christine Kim can be reached at FILLIN "SPE Phone?" \* MERGEFORMAT (571)272-8458 . The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /COLE LEON LINDSEY/ Examiner, Art Unit 2812 /CHRISTINE S. KIM/ Supervisory Patent Examiner, Art Unit 2812