Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Election/Restrictions
Applicant’s election without traverse of Group I and Species I in the reply filed on 4/24/2026 is acknowledged.
Claims 12-20 are withdrawn from further consideration pursuant to 37 CFR 1.142(b) as being drawn to nonelected Group II claims, there being no allowable generic or linking claim. In addition, claim 2 (as top and bottom gates are connected) and claim 6 is directed to Species II (merged gates, Fig. 9) embodiment. As such, claims 2, 6-11 are also withdrawn. Election was made without traverse in the reply filed.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
1. Claim(s) 1,3-5 is/are rejected under 35 U.S.C. 102a(1) as being anticipated by US 20230017350 A1 (Chanemougame, referenced as Chan).
Regarding claim 1, Chan shows (Fig. 6) a semiconductor device (400, para 33), comprising:
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a bottom transistor (as shown, lower semiconductor device, para 37) having a bottom gate (492, lower gate, para 37);
a top transistor (as shown, upper semiconductor device, para 37) having a top gate (492, upper gate, para 37) above the bottom gate, separated from the bottom transistor by a dielectric layer (418, para 37);
a conductive via (475, para 40) that extends through the top gate and the dielectric layer to contact the bottom transistor (as shown); and
a dielectric liner (474, para 40) between the conductive via and the top gate that electrically insulates the top gate from the conductive via.
Regarding claim 3, Chan shows (Fig. 6) wherein the top transistor further includes top source/drain structures (483, para 37) and the bottom transistor further includes bottom source/drain structures (482, para 37), and wherein the semiconductor device further includes source/drain contacts (not shown but obvious to a person of ordinary skill in the art) to the top source/drain structures and the bottom source/drain structures (not shown but obvious to a person of ordinary skill in the art.
Regarding claim 4, Chan shows (Fig. 6) wherein the conductive via (475, para 41) is offset with respect to the top gate (493).
Regarding claim 5, Chan shows (Fig. 6) wherein the dielectric liner (713, para 43) is formed from a low-k dielectric material (low-k spacer, para 43).
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to WASIUL HAIDER whose telephone number is (571)272-1554. The examiner can normally be reached M-F 9 a.m. - 6 p.m..
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/WASIUL HAIDER/Primary Examiner, Art Unit 2812
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