Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
OFFICE ACTION
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION. —The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 1-20 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Claim 1 is rejected because:
The limitation “symmetric quantum circuit respecting data characteristics on a series of quantum bits using symmetric quantum operations” as presented, is unclear with respect to its intended meaning or respecting and operation, i.e., respecting how, in what way, what operations.
The limitation “optimizing circuit parameters to minimize a performance metric” as presented, is unclear and does not make sense to one of ordinary skill in the art because one or ordinary skill in the understand that optimization is normally to improve performance, not to minimize performance.
(c) The limitation “optimizing circuit parameters to minimize a performance
metric” as presented, is unclear regarding what performance the Applicant
wants to minimize, what does metric represent?
(d) The limitation “new” in “new input data” as presented is contradicting and conflicting to claim 9 which recites “new input data is classical data”
(e)The limitation “generating output data over new input data” as presented
is unclear regarding input data from what/where, is output data generated based on input data, from input data, output data is new in terms of newly generated/ updated/ optimizes or input data is new.
Dependent claims 1-7 are rejected because they depend directly or indirectly from claim 1.
Claims 8-20 are rejected for the same reason.
Claims 2 and 9 are rejected because “classical data” in “classical data from a dataset” as presented is unclear regarding how data is considered classical or not classical, how data is considered classical or modern.
Claims 4 and 13 are rejected because “similar to fine-tune” as presented is unclear regarding what is considered similar fine tune.
Claims 4 and 13 are rejected because “or similar to fine-tune” is not positive recitation of the invention and it is unclear whether the limitation following “or similar to fine-tune” is actually implemented in the invention.
Claim 9 is rejected because it recites “the new input data is classical data” which is contradicting and conflicting to “new input data: in claim 8. How can input data both new and classical as claimed.
Claim 6 and 13 are rejected because “the quantum hardware” lacks antecedent basis.
Claim 15 is rejected because “the dataset” lacks antecedent basis.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) The claimed invention was patented, described in a printed publication, or in public use, on sale or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) The claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
INSOFAR THE LIMITATIONS ARE UNDERSTOOD AND GIVEN BROADEST REASONABLE INTERPRETATIONS.
Claims 1-5, 7-12 and 14 -20 are rejected under 35 U.S.C. 102(a) (2) as being anticipated by the prior art of record Zhang (US 2023/0144633)
Regarding claim 1 and similarly recited claim 8, the prior art discloses
A system for implementing symmetric quantum circuits (see one or more of par 88-98, 117-119), comprising:
a data processing module for processing input data from a data source (see one or more of fig 1-4, 6-9);
a quantum circuit construction module (fig 1, 9) for constructing a symmetric quantum circuit (see one or more of par 88-98, 117-119)) respecting data characteristics on a series of quantum bits (bit /qubit string, bit/qubit substring in one or more of abstract, summary, fig 2-9)) using symmetric quantum operations (symmetric quantum tasks/operations/ executions in one or more of par 88-98, 117-119 and/or fig 1-9);
an optimization module (fig 8) for optimizing circuit parameters to minimize a performance metric using an optimization technique (see one or more of abstract, summary, fig 2-9 and related tex.
Performance metric is one or more of cost function, measurement results, task results, computing results, quantum states/ tasks/ executions/ conditions, parameterized quantum circuit, parametric, expression, measurement result of tasks/ executions/ operations/states, measure quantum states.); and
an output generation module for generating output data over new input data (fig 1-7, 9 and related text)
(Claims 2, 9) wherein the data processing module reads classical data from a dataset (fig 1-4, 8-9).
(Claims 3, 10) wherein the symmetric quantum circuit construction module builds an equivariant variational quantum circuit (back ground, summary, fig 3, 5-7)
(Claim 4, 11) wherein the optimization module uses conjugate gradient descent or similar to fine-tune the parameters of the equivariant variational quantum circuit (par 99, 103, 111, 118, 137).
(Claims 5, 12) wherein the output generation module makes predictions over a new set of datapoints (predictions by quantum neural network (par 60))
(Claims 7, 14) wherein the symmetric quantum circuit provides faster convergence and training, better precision (abstract, summary, fig 2-5, 8-9 and related text).
(Claim 15) using the symmetries of the dataset to build the quantum circuit (see one or more of par 88-98, 117-119 and/or fig 1-4, 7-9 and related)
(Claim 16) Using training (see neural network in par 60) using a training set for the optimization of the quantum circuit.
(Claim 17) using a cost function (par 3) for the optimization of the quantum circuit.
(Claim 18) using quantum gates (par 28-29, 48-51,134-140, fig 6-7) in the construction of the quantum circuit.
(Claim 19) using a series of qubits (abstract, summary, fig 1-7, 9) in the construction of the quantum circuit.
(Claim 20) using quantum machine learning (par 60) in the implementation of the quantum circuits
Claims 1-16 and 18-20 are rejected under 35 U.S.C. 102(a) (2) as
being anticipated by the prior art of record Maksymov (US 2024/0127102)
Regarding claim 1 and similarly recited claim 8, the prior art discloses
A system for implementing symmetric quantum circuits (par 16-17, fig 4-9, 11), comprising:
a data processing module for processing input data from a data source (fig 1-5);
a quantum circuit construction module (fig 1-6) for constructing a symmetric quantum circuit (par 16-17, fig 4-9, 11), respecting data characteristics on a series of quantum bits (background, summary, fig 4, 7-10-11) using symmetric quantum operations (see tasks/ computations/ operations/ executions in fig 1-9);
An optimization module for optimizing circuit parameters to minimize a performance metric using an optimization technique (par 21-23, 46-50, 57-61, 66-67, 78, 81-88, 97-98, 105-118. performance metric is one or more of gains, measurement statistics, outcome measurements, data/dataset measurements, performance gains/improvements/measurements, optimal number of variants, variant output, accuracy measurements, symmetrization on performance, fidelity performance, metric performance, strongest/best improvements); and
an output generation module for generating output data over new input data (fig 2-5, 11).
(Claims 2, 9) wherein the data processing module reads classical data from a dataset (par 28, 36, 41, 43, 46, 57, 66-67, 98, 101, 105, 107, 109-118).
(Claims 3, 10) wherein the symmetric quantum circuit construction module builds an equivariant variational quantum circuit (par 7, 21, 22, 46-50, 55-59, 65-66, 71, 80-89, 95-101, 111).
(Claims 4, 11) wherein the optimization module uses conjugate gradient descent or similar to fine-tune the parameters of the equivariant variational quantum circuit (fine tune in terms of one or more of repeat quantum computation, creating/repetition variant implementations of quantum computation on specific hardware, so as to diminish errors and improve QC performance, sequences improve upon random samples, using machine learning (QML) circuits, training runs, repat measurements, variant executions (par 46, 48-49, 56-57, 86-87)).
(Claims 5, 12) wherein the output generation module makes predictions (predictions by quantum machine-learning (QML) circuits, machine learning algorithm, training runs (par 23, 43, 57-59, 63, 87-88) ) over a new set of datapoints.
(Claims 6, 13) wherein the quantum hardware is implemented on superconducting qubits (par 3, 96, 120), ion traps (par 3, 21, 33, 45, 84, 89), Rydberg atoms (par 26-27, 31-33, 45), photonic systems (par 3), and solid-state quantum dots (par 6, 24, 45, 127).
(Claims 7, 14)) wherein the symmetric quantum circuit provides faster convergence and training, better precision (par 21-23, 57, 86-88)
(Claim 15) using the symmetries of the dataset to build the quantum circuit (par 57, 101, 111, 116)
(Claim 16) Using training using a training set (par 23, 43, 57-59, 63, 87-88) for the optimization of the quantum circuit.
(Claim 18) using quantum gates (par 3, 19, 22-23, 49, 55, 59, 65, 80-90, 95, 110) in the construction of the quantum circuit.
(Claim 19) using a series of qubits (par 30, 46, 86, 98) in the construction of the quantum circuit.
(Claim 20) using quantum machine learning (par 23, 43, 57-59, 63, 87-88) in the implementation of the quantum circuits
Correspondence Information
Any inquiry concerning this communication or earlier communications from the examiner should be directed to PAUL DINH whose telephone number is 571-272-1890. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s Supervisor, Jack Chiang can be reached on 571-272-7483. The fax number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users.
To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format.
For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197(toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/PAUL DINH/ Primary Examiner, Art Unit 2851
Prosecution Insights