DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Priority
Receipt is acknowledged of certified copies of papers required by 37 CFR 1.55.
Information Disclosure Statement
The information disclosure statement (IDS) submitted on August 11, 2025 is in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statement is being considered by the examiner.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 1-19 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
The term “theoretical density” in claims 1 and 16 is a relative term which renders the claim indefinite. The term “theoretical density” is not defined by the claim, the specification does not provide a standard for ascertaining the requisite degree, and one of ordinary skill in the art would not be reasonably apprised of the scope of the invention. The “measurement density” is rendered indefinite by the relative term “theoretical density.” Thus, one of ordinary skill in the art would not be able to define the metes and bounds of the claimed invention.
Claims 2-15 and 17-19 are rejected based on their dependency on rejected claims 1 and 16.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claim(s) 1, 4-9, and 12-15, as best understood, is/are rejected under 35 U.S.C. 102(a)(2) as being anticipated by Kim (US Pub 2024/0213369).
In re claim 1, Kim discloses a semiconductor device (i.e. see at least Figures 2 and 6) comprising: a first electrode (i.e. 191); a second electrode (i.e. 192); an oxide semiconductor layer (i.e. 150) between the first electrode and the second electrode; a gate electrode (i.e. 170) spaced apart from the oxide semiconductor layer; and a gate insulating layer (i.e. 160) insulating the oxide semiconductor layer from the gate electrode, wherein a measurement density of the oxide semiconductor layer is about 90% or more of a theoretical density of the oxide semiconductor layer (i.e. in this case, it is implicit from Kim that the oxide semiconductor layer has a measurement density and that it is about 90% or more of a theoretical density, as best understood by one of ordinary skill in the art).
In re claim 4, Kim discloses wherein the oxide semiconductor layer comprises an oxide of at least one of In, Zn, Sn, Ga, or Hf (i.e. see at least paragraph 0084).
In re claim 5, Kim discloses wherein the oxide semiconductor layer comprises at least one of InGaZnO (i.e. see at least paragraph 0084).
In re claim 6, Kim discloses wherein the oxide semiconductor layer comprises In, Ga, and Zn, and a content of the In in the oxide semiconductor layer is greater than or equal to at least one of a content of the Ga or a content of the Zn (i.e. see at least paragraph 0084).
In re claim 7, Kim discloses wherein the oxide semiconductor layer comprises In, Ga, and Zn, and the In, the Ga, and the Zn included in the oxide semiconductor layer is represented by X:Y:Z (1≤X≤7, 1≤Y≤3, and 1≤Z≤3), respectively (i.e. see at least paragraph 0084).
In re claim 8, Kim discloses further comprising: a substrate (i.e. 110), wherein a longitudinal direction of the oxide semiconductor layer is parallel to a thickness direction of the substrate (i.e. see at least Figures 2 and 6).
In re claim 9, Kim discloses wherein each of the oxide semiconductor layer, the gate insulating layer, and the gate electrode are in line such that the oxide semiconductor layer, the gate insulating layer, and the gate electrode are stacked in a horizontal direction with respect to the surface of the substrate and the longitudinal direction of the oxide semiconductor layer, a longitudinal direction of the gate insulating layer, and a longitudinal direction of the gate electrode are perpendicular to a surface of the substrate (i.e. see at least Figures 2 and 6).
In re claim 12, Kim discloses wherein, when viewed in cross-section, the gate electrode is thicker than the gate insulating layer (i.e. see at least Figures 2 and 6).
In re claim 13, Kim discloses wherein the oxide semiconductor layer is rod-shaped, the gate insulating layer surrounds the oxide semiconductor layer, and the gate electrode surrounds the gate insulating layer (i.e. see at least Figures 1, 2, and 6).
In re claim 14, Kim discloses wherein the first electrode comprises at least Mo, Cr, Al, Cu, etc. (i.e. see at least paragraph 0057).
In re claim 15, Kim discloses further comprising: an oxide isolation layer (i.e. 180) adjacent to the gate electrode, the gate insulating layer, and the oxide semiconductor layer (i.e. see at least Figures 2 and 6).
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 16, 18, and 19, as best understood, is/are rejected under 35 U.S.C. 103 as being unpatentable over Wang et al (US Pub 2020/0044095) in view of Kim (US Pub 2024/0213369).
In re claim 16, Wang et al discloses an electronic device comprising: a plurality of memory cells (i.e. 401), wherein each of the memory cells comprises a switching element (i.e. 101), and a data storage element (i.e. 189) connected to the switching element (i.e. see at least Figure 4; paragraph 0039).
Wang et al does not explicitly disclose wherein the switching element comprises a first electrode, a second electrode, an oxide semiconductor layer between the first electrode and the second electrode; a gate electrode spaced apart from the oxide semiconductor layer; and a gate insulating layer insulating the oxide semiconductor layer from the gate electrode, wherein a measurement density of the oxide semiconductor layer is about 90% or more of a theoretical density of the oxide semiconductor layer.
However, Kim discloses a semiconductor device (i.e. see at least Figures 2 and 6) comprising: a first electrode (i.e. 191); a second electrode (i.e. 192); an oxide semiconductor layer (i.e. 150) between the first electrode and the second electrode; a gate electrode (i.e. 170) spaced apart from the oxide semiconductor layer; and a gate insulating layer (i.e. 160) insulating the oxide semiconductor layer from the gate electrode, wherein a measurement density of the oxide semiconductor layer is about 90% or more of a theoretical density of the oxide semiconductor layer (i.e. in this case, it is implicit from Kim that the oxide semiconductor layer has a measurement density and that it is about 90% or more of a theoretical density, as best understood by one of ordinary skill in the art).
The advantage is to provide a transistor capable of allowing high current to flow while occupying a small area (i.e. see at least paragraph 0007).
Thus, it would have been obvious to one of ordinary skill in the art at the time the invention was filed to have modified the electronic device as taught by Wang et al with wherein the switching element comprises a first electrode, a second electrode, an oxide semiconductor layer between the first electrode and the second electrode; a gate electrode spaced apart from the oxide semiconductor layer; and a gate insulating layer insulating the oxide semiconductor layer from the gate electrode, wherein a measurement density of the oxide semiconductor layer is about 90% or more of a theoretical density of the oxide semiconductor layer as taught by Kim in order to provide a transistor capable of allowing high current to flow while occupying a small area.
In re claim 18, Wang et al, as discussed above, does not explicitly disclose wherein the oxide semiconductor layer comprises In, Ga, and Zn, and a content of the In in the oxide semiconductor layer is greater than or equal to at least one of a content of the Ga or a content of the Zn.
However, Kim discloses wherein the oxide semiconductor layer comprises In, Ga, and Zn, and a content of the In in the oxide semiconductor layer is greater than or equal to at least one of a content of the Ga or a content of the Zn (i.e. see at least paragraph 0084).
The advantage is to provide a transistor capable of allowing high current to flow while occupying a small area (i.e. see at least paragraph 0007).
Thus, it would have been obvious to one of ordinary skill in the art at the time the invention was filed to have modified the electronic device as taught by Wang et al with wherein the oxide semiconductor layer comprises In, Ga, and Zn, and a content of the In in the oxide semiconductor layer is greater than or equal to at least one of a content of the Ga or a content of the Zn as taught by Kim in order to provide a transistor capable of allowing high current to flow while occupying a small area.
In re claim 19, Wang et al, as discussed above, does not explicitly disclose wherein the oxide semiconductor layer comprises In, Ga, and Zn, and the In, the Ga, and the Zn included in the oxide semiconductor layer is represented by X:Y:Z (1≤X≤7, 1≤Y≤3, and 1≤Z≤3), respectively.
However, Kim discloses wherein the oxide semiconductor layer comprises In, Ga, and Zn, and the In, the Ga, and the Zn included in the oxide semiconductor layer is represented by X:Y:Z (1≤X≤7, 1≤Y≤3, and 1≤Z≤3), respectively (i.e. see at least paragraph 0084).
The advantage is to provide a transistor capable of allowing high current to flow while occupying a small area (i.e. see at least paragraph 0007).
Thus, it would have been obvious to one of ordinary skill in the art at the time the invention was filed to have modified the electronic device as taught by Wang et al with wherein the oxide semiconductor layer comprises In, Ga, and Zn, and the In, the Ga, and the Zn included in the oxide semiconductor layer is represented by X:Y:Z (1≤X≤7, 1≤Y≤3, and 1≤Z≤3), respectively as taught by Kim in order to provide a transistor capable of allowing high current to flow while occupying a small area.
Allowable Subject Matter
Claims 2, 3, 10, 11, and 17 would be allowable if rewritten to overcome the rejection(s) under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), 2nd paragraph, set forth in this Office action and to include all of the limitations of the base claim and any intervening claims.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
a. Wu et al (US Pub 2024/0355933)
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/ANTHONY HO/Primary Examiner, Art Unit 2817
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