Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
DETAILED ACTION
This office action is in response to the Applicant Election filled on 03/12/2026. Currently, claims 1-20 are pending in the application. Claims 4-7, 9-11 and 13-20 are withdrawn from Consideration.
Election/Restrictions
Applicant's election with traverse of Group I and Species IA, claims 1-3, 8 and 12, in the reply filed on 03/12/2026 is acknowledged.
The first traversal is on the ground(s) that the examination of all of claims 1-20 would not present an undue burden on the Examiner, and respectfully request reconsideration and withdrawal of the Restriction Requirement.
This is not found persuasive and the Examiner has already established burden (as defined in M.P.E.P. 808.02) in the restriction requirement dated 03/09/2026. There is a search and/or examination burden for the patentably distinct species or device/method claims, wherein they require a different field of search (e.g., searching different classes/subclasses or electronic resources or non-patent language, or deploying different search queries); and/or the prior art applicable to one invention would not likely be applicable to another; and/or the inventions are likely to raise different non-prior art issues under 35 U.S.C 101 and/or 35 U.S.C 112, first paragraph. Therefore, the requirement is still deemed proper and is therefore made FINAL.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale or otherwise available to the public before the effective filing date of the claimed invention.
A person shall be entitled to a patent unless –
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claims 1-3, 8 and 12 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by CHO et al (US 20180068958 A1).
Regarding claim 1, Figure 3 of CHO discloses a semiconductor package, comprising:
a lower-layer structure (100-200, [0014]) including a substrate (100, [0014]);
a first chip (130, [0017]) including bumps (136, [0019]) on an active surface (bottom surface that is facing 120) thereof, the first chip being electrically connected to the substrate (100) via the bumps (136);
an upper-layer structure (150, [0021]) formed of a first molding material, the first molding material covering an inactive surface (top surface of 130 in the Figure 3) of the first chip (130) and surrounding at least a portion of a lateral surface (side surfaces) of the first chip (130), the inactive surface (top surface of 130 in the Figure) of the first chip being opposite to the active surface (bottom surface of 130) of the first chip (130); and
a middle-layer (140, [0020]) structure including at least one interlayer (140), the at least one inter layer being formed of a second molding material (polymer adhesive, [0020]) different from the first molding material (140 is adhesive polymer and 150 is epoxy resin), the middle-layer (140) structure being between the lower-layer structure (100-200) and the upper-layer structure (150) and filling a space between the lower-layer structure (100-200) and the upper-layer structure (150).
Regarding claim 2, Figure 3of CHO discloses that the semiconductor package as claimed in claim 1, wherein the first molding material (150, [0021]) includes a rigid material or a flexible material, and the second molding material includes a flexible material (140, [0020]).
Regarding claim 3, Figure 3of CHO discloses that the semiconductor package as claimed in claim 2, wherein the second molding material (140, [0020]) covers the active surface (bottom surface of 130 in the Figure 3) of the first chip (130), and surrounds a remaining portion of the lateral surface of the first chip (130), the remaining portion of the lateral surface of the first chip (130) being a portion excluding the at least a portion of the lateral surface of the first chip.
Regarding claim 8, Figure 3of CHO discloses that the semiconductor package as claimed in claim 2, wherein the upper-layer structure (150, [0021]) has a first thickness, the middle-layer structure (140, [0020]) has a second thickness, and a ratio of the first thickness to the second thickness is configured to control a warpage of the semiconductor package ([0038]).
Regarding claim 12, Figure 3of CHO discloses that the semiconductor package as claimed in claim 2, wherein the first molding material (150, [0021]) includes the flexible material, the first chip includes a plurality of first chips (130), and the semiconductor package further includes: a plurality of second chips (120, [0017]), stacked on the plurality of first chips, respectively, wherein the plurality of first chips and the plurality of second chips (120) respectively have sizes and stacking forms different from one another to form a complex stacking structure ([0003]).
Examiner Notes
A reference to specific paragraphs, columns, pages, or figures in a cited prior art reference is not limited to preferred embodiments or any specific examples. It is well settled that a prior art reference, in its entirety, must be considered for all that it expressly teaches and fairly suggests to one having ordinary skill in the art. Stated differently, a prior art disclosure reading on a limitation of Applicant's claim cannot be ignored on the ground that other embodiments disclosed were instead cited. Therefore, the Examiner's citation to a specific portion of a single prior art reference is not intended to exclusively dictate, but rather, to demonstrate an exemplary disclosure commensurate with the specific limitations being addressed. In re Heck, 699 F.2d 1331, 1332-33,216 USPQ 1038, 1039 (Fed. Cir. 1983) (quoting In re Lemelson, 397 F.2d 1006, 1009, 158 USPQ 275, 277 (CCPA 1968)). In re: Upsher-Smith Labs. v. Pamlab, LLC, 412 F.3d 1319, 1323, 75 USPQ2d 1213, 1215 (Fed. Cir. 2005); In re Fritch, 972 F.2d 1260, 1264, 23 USPQ2d 1780, 1782 (Fed. Cir. 1992); Merck& Co. v. BiocraftLabs., Inc., 874 F.2d 804, 807, 10 USPQ2d 1843, 1846 (Fed. Cir. 1989); In re Fracalossi, 681 F.2d 792,794 n.1, 215 USPQ 569, 570 n.1 (CCPA 1982); In re Lamberti, 545 F.2d 747, 750, 192 USPQ 278, 280 (CCPA 1976); In re Bozek, 416 F.2d 1385, 1390, 163 USPQ 545, 549 (CCPA 1969).
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to KHAJA AHMAD whose telephone number is (571)270-7991. The examiner can normally be reached on Monday-Friday, 8:00 AM - 5:00 PM (Eastern Time).
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, GAUTHIER STEVEN B, can be reached on (571)270-0373. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/KHAJA AHMAD/Primary Examiner, Art Unit 2813
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