DETAILED ACTION Notice of Pre-AIA or AIA Status The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA. Claim Rejections - 35 USC § 102 The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action: A person shall be entitled to a patent unless – (a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention. Claim(s) 1 -20 is/are rejected under 35 U.S.C. 102(a)(2) as being anticipated by Reboh et al. (20 25 /0 194238 ). The applied reference has a common applicant with the instant application. Based upon the earlier effectively filed date of the reference, it constitutes prior art under 35 U.S.C. 102(a)(2). This rejection under 35 U.S.C. 102(a)(2) might be overcome by: (1) a showing under 37 CFR 1.130(a) that the subject matter disclosed in the reference was obtained directly or indirectly from the inventor or a joint inventor of this application and is thus not prior art in accordance with 35 U.S.C. 102(b)(2)(A); (2) a showing under 37 CFR 1.130(b) of a prior public disclosure under 35 U.S.C. 102(b)(2)(B) if the same invention is not being claimed; or (3) a statement pursuant to 35 U.S.C. 102(b)(2)(C) establishing that, not later than the effective filing date of the claimed invention, the subject matter disclosed in the reference and the claimed invention were either owned by the same person or subject to an obligation of assignment to the same person or subject to a joint research agreement. Regarding claim s 1 and 16 , Reboh (Fig. 9 ) discloses a semiconductor structure comprising: a dielectric wall structure 26 directly contacting and physically separating a first stacked transistor (on the left side of the center #26) from a second stacked transistor (on the right side of the center #26) ([0024]) ; a merged top gate electrode 36 extending over the dielectric wall structure 26 and surrounding a top semiconductor channel region 24 of the first stacked transistor and a top semiconductor channel region 24 of the second stacked transistor (Fig. 9, [0025]) ; a bottom gate electrode 32 of the first stacked transistor surrounding a bottom semiconductor channel region 18 of the first stacked transistor; a bottom gate electrode 32 of the second stacked transistor surrounding a bottom semiconductor channel region 18 of the second stacked transistor ([0025]) ; a first frontside bottom gate contact structure 38 contacting the bottom gate electrode 32 of the first stacked transistor; a second frontside bottom gate contact structure 38 contacting the bottom gate electrode 32 of the second stacked transistor ([0027-0028]) ; and a frontside back-end-of-the-line (BEOL) interconnect structure 44 located over the first stacked transistor and the second stacked transistor and in electrical contact with the first frontside bottom gate contact structure 44 and the second frontside bottom gate contact structure 44 (Fig. 9, [0028] ) . Regarding claim s 2 , 12 and 1 7 , Reboh (Fig. 9 ) discloses wherein the bottom semiconductor channel region 18 of the first stacked transistor and the bottom semiconductor channel region 18 of the second stacked transistor have a first width, and the top semiconductor channel region 24 of the first stacked transistor and the top semiconductor channel region 24 of the second stacked transistor have a second width, wherein the second width is less than the first width. Regarding claim s 3 and 1 8 , Reboh (Fig. 9 ) discloses wherein the electrical contact of the frontside BEOL interconnect structure 44 with the first frontside bottom gate contact structure 42B is through a first bottom gate middle-of-the-line (MOL) contact structure 40 ([0027]) , and the electrical contact of the frontside BEOL interconnect structure 44 with the second frontside bottom gate contact structure 42A is through a second bottom gate MOL contact structure contact structure 40 , wherein the first bottom gate MOL contact structure 42B and the second bottom gate MOL contact structure 42A are embedded in a MOL dielectric layer 40 ([0027-0028]) . Regarding claim s 4 -5 and 1 3 , Reboh (Fig. 9 ) discloses further comprising a frontside BEOL interconnect structure located above the first stacked transistor and the second stacked transistor; and a shared top gate middle-of-the-line (MOL) contact structure electrically connecting the merged top gate electrode to the frontside BEOL interconnect structure. Regarding claim 6 , Reboh (Fig. 12 ) discloses wherein the first frontside bottom gate contact structure 52 is a first non-shared frontside bottom gate contact structure, and the second frontside bottom gate contact structure 52 is a second non-shared frontside bottom gate contact structure ([0031]) . Regarding claim 7 , Reboh (Fig. 9 ) discloses wherein the first frontside bottom gate contact structure 38 is a first shared frontside bottom gate contact structure, and the second frontside bottom gate contact structure 38 is a second shared frontside bottom gate contact structure. Regarding claim 8 , Reboh (Fig. 10 ) discloses further comprising a backside interconnect structure 50 located beneath the first stacked transistor and the second stacked transistor ([0028]) . Regarding claim s 9 and 14 , Reboh (Fig. 11 ) discloses further comprising a frontside gate cut structure 34 located on each side of the dielectric wall structure 26 , wherein the frontside gate cut structure 34 is adjacent to the merged top gate electrode 36 that is present on both sides of the dielectric wall structure 26 ([0025]) . Regarding claim s 1 0 and 15 , Reboh (Fig. 9 ) discloses further comprising a backside gate cut structure 48 contacting the frontside gate cut structure 34 that is present on at least one side of the dielectric wall structure 26 ([0027]) . Regarding claim 1 1 , Reboh (Fig. 11 ) discloses a semiconductor structure comprising: a dielectric wall structure 26 directly contacting and physically separating a first stacked transistor (on the left side of the center #26) from a second stacked transistor (on the right side of the center #26) ([0024]) ; a merged top gate electrode 36 extending over the dielectric wall structure 26 and surrounding a top semiconductor channel region 24 of the first stacked transistor and a top semiconductor channel region 24 of the second stacked transistor (Fig. 9, [0025]) ; a bottom gate electrode 32 of the first stacked transistor surrounding a bottom semiconductor channel region 18 of the first stacked transistor; a bottom gate electrode 32 of the second stacked transistor surrounding a bottom semiconductor channel region 18 of the second stacked transistor ([0025]) ; a first backside bottom gate contact structure 48 contacting the bottom gate electrode 32 of the first stacked transistor ([0027]) ; a second backside bottom gate contact structure 48 contacting the bottom gate electrode 32 of the second stacked transistor; and a backside interconnect structure 50 located beneath the first stacked transistor and the second stacked transistor and in electrically contact with the first backside bottom gate contact structure 48 and the second backside bottom gate contact structure 48 (Fig. 11) . Regarding claim 1 9 , Reboh (Fig. 9 ) discloses further comprising a first top gate MOL contact structure 42A electrically connecting the first top gate electrode 36 to the frontside BEOL interconnect structure 44 , and a second top gate MOL contact structure 42 B electrically connecting the second non top gate electrode 38 to the frontside BEOL interconnect structure 44 . Regarding claim 20 , Reboh (Fig. 11 ) discloses further comprising a frontside gate cut structure 34 located on each side of the dielectric wall structure 26 , wherein the frontside gate cut structure 34 located on a first side of the dielectric wall structure 26 is adjacent to the first top gate electrode 36 and the frontside gate cut structure 34 located on a second side of the dielectric wall structure 26 is adjacent to the second top gate electrode 36 . Conclusion Any inquiry concerning this communication or earlier communications from the examiner should be directed to FILLIN "Enter examiner's name" \* MERGEFORMAT THERESA T DOAN whose telephone number is FILLIN "Phone number" \* MERGEFORMAT (571)272-1704 . The examiner can normally be reached on FILLIN "Work schedule?" \* MERGEFORMAT Monday, Tuesday, Wednesday and Thursday from 7:00AM - 3:00PM . Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice . If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, FILLIN "SPE Name?" \* MERGEFORMAT WAEL FAHMY can be reached on FILLIN "SPE Phone?" \* MERGEFORMAT (571) 272-1705 . The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. 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