DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 1-20 is/are rejected under 35 U.S.C. 103 as being unpatentable over U.S. Patent Application Publication 2022/0113483 to Kalman et al.
In regards to claims 1, 11 and 20 , Kalman recites a chip package/manufacturing method (Figure 3A), comprising: an interposer (313); a plurality of semiconductor chips (first 311a & second 311b) optically connected to the interposer, wherein the plurality of semiconductor chips comprises at least four [0036] said semiconductor chips; and an optical interconnect chip (325 layer) connected to the interposer; wherein each of the plurality (first and second) of semiconductor chips is configured to be optically connected to the optical interconnect chip via the interposer, to realize optical signal communication between any two of the plurality of semiconductor chips. Although Kalman does not expressly recite the optical interconnect chip to be optically connected to the interposer, Kalman does recite an optical chip to chip interconnects [0010], the integrated circuit chips having optical components and being semiconductor chips [0011, 0015, 0036, 0039]. Since Kalman teaches optical semiconductor chips and optical chip to chip interconnectors, it would have been obvious before the effective filing date to a person having ordinary skill in the art to have provided a completely optical system since pure optical systems offer a larger bandwidth and speed and do not require the conversion between electrical and optical signals.
In regards to claims 2 and 12, modified Kalman recite the interposer is configured to carry the plurality of semiconductor chips and the optical interconnect chip. [0036, 0039]
In regards to claims 3 and 13, modified Kalman does not expressly recite the interposer comprises a plurality of first waveguides, each of the plurality of semiconductor chips comprises a second waveguide optically connected to a corresponding one of the first waveguides, and the optical interconnect chip comprises a plurality of third waveguides each optically connected to two of the first waveguides, wherein the plurality of semiconductor chips comprises a first semiconductor chip and a second semiconductor chip, the second waveguide of the first semiconductor chip is optically connected to the first waveguide corresponding to the first semiconductor chip, the second waveguide of the second semiconductor chip is optically connected to the first waveguide corresponding to the second semiconductor chip, and the first waveguide corresponding to the first semiconductor chip is optically connected to the first waveguide corresponding to the second semiconductor chip through one of the plurality third waveguides. However, placing a waveguide in order to transmit an optical signal in the modified optical chip package in place of conversion circuitry, such as 317 and 323, would have been an obvious matter of common skill and design choice in a modified optical chip package since optical waveguides are well known components in the optical art for transmitting optical signals.
In regards to claims 4-6 and 14-16, modified Kalman recites the second waveguide is optically connected to the corresponding one of the first waveguides, and the third waveguides (325) are optically connected to the first waveguides, the plurality of semiconductor chips is optically connected to the interposer and the optical interconnect chip is optically connected to the interposer. Although Kalman does not expressly recite coupling through at least one of evanescent coupling and grating coupler coupling, Kalman does recite coupling though light collection optics. Grating couplers and evanescent couplings are examples of light collection optics that provide the advantage of manipulating light and coupling light in a pure optical device. Therefore, it would have been obvious before the effective filing date to a person having ordinary skill in the art to have provided coupling through at least one of evanescent coupling and grating coupler coupling.
In regards to claims 7 and 17, modified Kalman recites the interposer comprises at least one of a semiconductor substrate, a glass substrate, or a ceramic substrate. [0042]
In regards to claims 8 and 18, modified Kalman recites the first waveguides of the interposer comprise at least one of polymer waveguides, glass waveguides, silicon waveguides, or silicon nitride waveguides.
In regards to claims 9, 10 and 19, modified Kalman recites the plurality of third waveguides are arranged in at least two layers, wherein: the at least two layers comprise a first layer and a second layer; the plurality of semiconductor chips further comprises a third semiconductor chip [0036] and a fourth semiconductor chip [0036]; the second waveguide of the third semiconductor chip is optically connected to the first waveguide corresponding to the third semiconductor chip, the second waveguide of the fourth semiconductor chip is optically connected to the first waveguide corresponding to the fourth semiconductor chip, the first waveguide corresponding to the third semiconductor chip is optically connected to the first waveguide corresponding to the fourth semiconductor chip through one of the plurality third waveguides, the third waveguide optically connected to the first waveguide corresponding to the first semiconductor chip and the first waveguide corresponding to the second semiconductor chip is in the first layer, and the third waveguide optically connected to the first waveguide corresponding to the third semiconductor chip and the first waveguide corresponding to the fourth semiconductor chip is in the second layer.
References Cited
The references cited made of record and not relied upon is considered pertinent to applicant’s disclosure.
Inventorship
This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to TINA M WONG whose telephone number is (571)272-2352. The examiner can normally be reached M-F 8:30-5:30.
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/TINA WONG/Primary Examiner, Art Unit 2874